Besides direct or FOWLER-NORDHEIM tunneling, which are one-step tunneling
processes, defects in the dielectric layer give rise to tunneling processes
based on two or more steps. This tunneling component is mainly observed after
writing-erasing cycles in electrically erasable programmable
read-only-memories (EEPROMs). It is therefore assumed that traps arise in the
dielectric layer due to the repeated high voltage stress. The increased
tunneling current at low bias is called stress-induced leakage current (SILC)
and is mainly responsible for the degradation of the retention time of
non-volatile memory devices [187]. It is now generally accepted
that it is caused by inelastic trap-assisted tunnel transitions and that the
traps are created by the electric high-field stress during the writing and
erasing
processes [187,188,189,190,191,192]. SILC
has been widely studied and modeled in MOS
capacitors [193,194,195] and EEPROM
devices [196].
This section gives a brief overview of trap-assisted tunneling models,
describes two frequently encountered models (CHANG's and
IELMINI's model) and elaborates on one of the most sophisticated
models which was originally proposed by JIMENEZ et al.. The adaption of this
model to allow its inclusion in the device simulator MINIMOS-NT is described in
some detail.
Subsections
A. Gehring: Simulation of Tunneling in Semiconductor Devices
