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5.1.2.3 Effect of the Dielectric Thickness on the Channel Tunneling

The physical thickness of the dielectric has the largest impact on the gate current density, as shown in Fig. 5.5. Increasing the gate dielectric thickness by 0.4nm leads to a decrease of all tunneling current components by several orders of magnitude.
Figure 5.5: Electron (left) and hole (right) current density in an nMOS (top) and a pMOS (bottom) with different thickness of the dielectric layer. Gate polysilicon doping is 5e20 cm-3, substrate doping is 5e18 cm-3.
\includegraphics[width=.49\linewidth]{figures/nMosThicknessElectrons} \includegraphics[width=.49\linewidth]{figures/nMosThicknessHoles}
\includegraphics[width=.49\linewidth]{figures/pMosThicknessElectrons} \includegraphics[width=.49\linewidth]{figures/pMosThicknessHoles}


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A. Gehring: Simulation of Tunneling in Semiconductor Devices