5.1.2 Channel Tunneling

In this section the effects of various device parameters on the gate leakage of MOS capacitors are studied. This is equivalent to tunneling in MOS transistors, if only channel tunneling (n-p or p-n) is considered and the source, drain, and bulk contacts are grounded. The parameters investigated are

• the doping of the polysilicon gate contact,
• the doping of the substrate,
• the thickness of the dielectric layer,
• the barrier height of the dielectric,
• the carrier mass in the dielectric,
• the dielectric permittivity, and
• the lattice temperature.

The typical shape of the gate current density in turned-off nMOS and pMOS devices is depicted in Fig. 5.2. A SiO$_2$ gate dielectric thickness of 2nm and an acceptor or donor doping of 5e17 cm-3 and polysilicon gates was chosen. In the nMOS device the majority electron tunneling current always exceeds the hole tunneling current due to the lower electron mass and barrier height (3.2eV instead of 4.65eV for holes). In the pMOS capacitor, however, the majority hole tunneling exceeds electron tunneling only for negative and low positive bias. For positive bias the conduction band electron current again dominates due to its much lower barrier height [251].

Figure 5.2: Channel tunneling regions in an nMOS (left) and a pMOS (right). The insets show the approximate shape of the band edge energies.

Subsections

• 5.1.2.1 Effect of the Polysilicon Gate Doping on the Channel Tunneling
• 5.1.2.2 Effect of the Substrate Doping on the Channel Tunneling
• 5.1.2.3 Effect of the Dielectric Thickness on the Channel Tunneling
• 5.1.2.4 Effect of the Barrier Height on the Channel Tunneling
• 5.1.2.5 Effect of the Carrier Mass on the Channel Tunneling
• 5.1.2.6 Effect of the Dielectric Permittivity on the Channel Tunneling
• 5.1.2.7 Effect of the Lattice Temperature on the Channel Tunneling
• 5.1.2.8 Comparison to Measurements
• 5.1.2.9 Validity of Compact Models

A. Gehring: Simulation of Tunneling in Semiconductor Devices