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 Previous: 5.1.3.2 Effect of the Substrate Doping on the   Up: 5.1.3 Source and Drain Extension Tunneling   Next: 5.1.3.4 Effect of the Lattice Temperature on the

5.1.3.3 Effect of the Dielectric Permittivity on the Source and Drain Extension Tunneling

Fig. 5.14 shows the effect of the dielectric permittivity on the extension region gate current density. In contrast to the channel-tunneling case, the low-bias regime is not influenced by the permittivity. Furthermore, the influence on the majority tunneling current component depends on the bias: The electron tunneling component in the nMOS decreases for negative bias and increases for positive bias. The hole tunneling component in the pMOS shows exactly the inverse trend.

Figure 5.14: Effect of the dielectric permittivity $ \kappa / \kappa _0$ on the electron tunneling current (left) and the hole tunneling current (right) in the source and drain extension region of an nMOS (top) and a pMOS (bottom) with 2 nm dielectric thickness and 5e18 cm-3 substrate doping.
\includegraphics[width=.49\linewidth]{figures/ninElectronsPermittivity} \includegraphics[width=.49\linewidth]{figures/ninHolesPermittivity}
\includegraphics[width=.49\linewidth]{figures/pipElectronsPermittivity} \includegraphics[width=.49\linewidth]{figures/pipHolesPermittivity}

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A. Gehring: Simulation of Tunneling in Semiconductor Devices