In the absence of independent means of verification,
the extraction methodology is validated by applying it on capacitance
data generated using simulation with a known TPS profile.
The extracted profile is then compared to the original one.
A TPS profile with known knots location is used to eliminate errors
associated with the TPS approximation. Fig. 4.14 and Fig. 4.15
show the original, starting, and extracted lateral net doping profiles at
the SiO
/Si interface (Fig. 4.14), and at 
depth into
silicon (Fig. 4.15). As seen, the agreement is very good in both cases.
However, the fit accuracy decreases slightly in the high concentration S/D region (Fig. 4.14) and as we move into the inner diode regions (Fig. 4.15). This is caused by the inability to uncover the dopant atoms in those regions due to the limited capability of the gate to deplete the region of carriers under accumulation bias without oxide breakdown in the first case, and to the screening effects of the intermediate dopant layers in the second. In other words, we cannot ``probe'' those portions of the doping profile. It is noted that the junction delineation is very good.
Figure 4.14:
Comparison of original (dashed), initial guess (dotted),
and extracted (solid) net doping at the SiO/Si interface for the
simulation experiment.
Figure 4.15: Comparison of original (dashed), initial guess (dotted),
and extracted (solid) net doping at depth into silicon for
the simulation experiment.