4.4.1 FinFET Structure

Fig. 4.21 shows the basic structure of a FinFET published in [163]. The device is formed on a thin silicon on insulator (SOI) finger termed fin. On the top of the silicon fin nitride has been deposited on a thin pad oxide to protect the silicon fin during gate poly-SiGe etching. The gates are formed at the vertical sides of the fin using a thin gate oxide layer. Gate work-function tailoring is essential to adjust the threshold voltage. Therefore, for the gate material poly-SiGe has been chosen. The crucial geometric device dimensions are:

• $L_{\mathrm{g}}$: printed gate length.
• $L_{\mathrm{eff}}$: effective gate length which is determined by the distance of the junctions.
• $T_{\mathrm{fin}}$: Height of the fin.
• $W_{\mathrm{fin}}$: Width of the fin which is the distance between the gate oxides of the two gates.

Figure 4.21: Views of the simulated FinFET.

The geometrical channel width is given by $2 T_{\mathrm{fin}}$ for one fin since both channels have to be taken into account. To obtain higher drive currents additional fins must be applied in parallel. Fig. 4.22 shows a FinFET using three fins. Thus, with this structure a three times higher drive current can be achieved. The gate comb is formed as a small stripe which contacts the gates of all fins.

Figure 4.22: FinFET structure with three fingers.