The simulated structure is shown in Fig. 4.23. It is a one fin device and the geometry was defined as depicted in Fig. 4.21. The device dimensions are taken from a real manufactured device described in . According to Fig. 4.21 the device dimensions chosen are: , , , , and .
Fig. 4.24 gives the - characteristics of the device. Good agreement can be found with the measurement data given in . The threshold voltage is . The current is normalized by the channel width which is given by . The low current of the FinFET is due to a high series resistance of the contacts caused by the high source/drain extension resistance  and a degraded electron mobility caused by the silicon fin sidewall roughness generated by dry etching processes .
Contour lines of the electron current density are shown in Fig. 4.25 for . The channels are formed at the sides of the fin. The maximum current appears near the surface, because quantum effects have not been taken into account .
Fig. 4.26 gives a more closer view at the channel region of the fin. The contour lines show the electron current density in the channel. The corner effects can clearly be seen at the edges of the channel region. This is caused by the electric field which is much higher in the corners. The corners can be seen as transistors in parallel to the main transistor. Because of the higher electric field the corner transistor turns on earlier than the main transistor . Therefore to properly predict the device performance three-dimensional simulations are mandatory.
Robert Klima 2003-02-06