Because of the easy integration with CMOS, the MTJ-based logic gates are generalizable to STT-MRAM-based stateful logic architectures by using hybrid CMOS/MTJ technology. By utilizing the access transistors of the 1T/1MTJ cells not only as on-off switches but also as voltage-controlled resistors, the circuit implementation of the structural asymmetry in the improved implication logic gates is addressed. This STT-MRAM-based logic implementation enables non-volatile logic fan-out and provides high flexibility with regard to the use of arbitrary MTJs as input and output. The implementation is computationally complete, has a simple circuit structure (STT-MRAM), delocalizes computational execution, and eliminates the need for intermediate circuitry. It also enables parallel non-volatile computations and, therefore, it is suited for complex logic functions evaluation and opens an alternative path towards zero-standby power logic systems, shifting away from the Von Neumann architecture by eliminating the need for data transfer between separate memory and logic units to shorten the interconnection delay.

A performance analysis and comparison of the MRAM-based implication and reprogrammable logic architectures is presented. It is shown that for the intrinsic (N)AND and (N)OR operations, the reprogrammable gate requires slightly less power than the corresponding implication-based implementation. However, MRAM-based implication logic enables a more reliable logic behavior as compared to the reprogrammable gates. Furthermore, the implication architecture outperforms the reprogrammable gate for more complex logic functions and is thus the implementation of choice for large-scale logic circuits. As an example, the implementation of a stateful full adder based on the STT-MRAM implication logic architecture is described. Compared to the previous implication-based design, the total number of logic steps is decreased by about 30% and thus less execution time and energy are required. The possible tradeoffs to optimize the execution time, energy consumption, and the reliability of the reprogrammable and implication MRAM-based stateful logic architecture are also described. It is shown that a combined reprogrammable-implication logic architecture minimizes the total number of the required logic steps and thus the energy consumptions. However, it decreases the reliability of the MRAM-based computation. It is demonstrated that the parallelization of MRAM-based computations can significantly reduce the execution time.