5  Stateful STT-MRAM Arrays for Large-Scale Logic Circuits

5.1 Overview
5.2 Implementation of the Reprogrammable Architecture
5.3 Implementation of the Improved Implication Architecture
5.3.1 Structural Asymmetry
5.3.2 Addressing the Asymmetry Issue
5.4 Complex Logic Functions Using Improved Symmetric Implication
5.4.1 Non-Volatile Logic Fan-Out
5.4.2 Stateful STT-MRAM-based Full Adder
5.5 Toward High Performance STT-MRAM-Based Stateful Logic
5.5.1 Combined Reprogrammable-Implication Logic
5.5.2 Parallel STT-MRAM-Based Computation
5.6 Summary