3.1  Overview


Figure 3.1.: Separated logic and memory units in a two-dimensional CMOS logic system.

At present, the most commonly used logic circuits consist of memory units for data storage and separated logic units for holding data and performing arithmetic and logical operations, which are typically implemented based on CMOS technology (Fig. 3.1). These CMOS-based logic circuits retain information as long as power is applied (volatility) and any power supply interruption can cause loss of information. As the dimensions of the CMOS transistors shrink down the leakage currents increase. As a result, the continuously powered memory units cause large static (standby) power consumptions in CMOS-based logic circuits. In fact, they have become as large as the dynamic power consumption [3]. Furthermore, the increasing length of the interconnections between logic and memory limits the chip performance and results in the increment of both power and interconnection delay.

As one of the solutions of the above-described problems, non-volatility has been introduced to the logic circuit. Non-volatile elements retain the information and the logical state of the system is not lost, if the power supply is interrupted. In addition, distributing non-volatile memory elements over the CMOS logic circuit plane (logic-in-memory architecture [50]) combines logic and memory elements and allows extremely low standby power consumption as well as instant start-up, by holding the information in the non-volatile elements and eliminating the need for refreshing pulses which are critical for CMOS-based memory elements. In addition, the use of non-volatile memory devices for novel computational architectures enables the application of the same elements as latches and logic gates, called stateful logic [75]. Stateful logic inherently realizes logic-in-memory circuits with zero-standby power, extends non-volatile electronics from memory to logic applications, and allows to shorten the interconnection delay. This opens the door for innovation in computational paradigms by shifting away from the Von Neumann architecture which transfers the information back and forth between the separated memory and logic units [26, 75, 55, 56, 58, 59].