Chapter 6
Summary and Outlook

One of the key paradigms to enhance and improve the capabilities and performance of ICs is 3D integration. The work presented in this thesis advances the understanding of the mechanical reliability of open TSVs, which are one of the central components in 3D integration. The TSV is essentially a vertical conductor connecting the top and the bottom of a silicon substrate in a stacked die. Because TSVs have the task of electrically connecting components in an IC, its reliability is a fundamental aspect to examine. The TSV reliability deals with the tolerable thermal budget, mechanical stability, process variability, and electromigration. Each of these aspects can seriously impact and compromise the performances of the IC. Therefore, all reliability aspects have to be thoroughly investigated. The work presented here is focused on the mechanical stability of open TSVs. TSV interconnects can mechanically fail due to tensile rupture, creep failure, and fatigue causing an open circuit in the conducting line.

Before mass production is viable, a variety of experimental, modeling, and analysis techniques must be employed in order to investigate all potential failure conditions. Using experimental analysis and simulation techniques, TSVs under different scenarios can be examined and the most reliable configuration of the TSV structure for a desired application can be obtained.

In this thesis FEM, a numerical method which permits to analyze different multiphysical problems, has been employed. Mechanical simulations have been performed for open TSVs, which frequently use conducting materials based on W or Cu metalization technology. The presented work is focused on open W-lined TSVs, which are already used in mass production in image sensors to transport the sensor signal between vertically-stacked dies. W is used when the IC is subjected to many temperature cycles because it has a smaller thermal expansion coefficient compared to Cu. Therefore a smaller stress variation at the interfaces between W and Si under thermal cycling results in a higher structure stability. However, during the deposition process the W develops a very high intrinsic stress, which can be problematic for the stability of the TSV and, furthermore, for the entire IC. For this reason the potential mechanical problems in open W-lined TSVs have been investigated. Results of this investigation extend the state-of-the-art knowledge about the failure modes in such structures.

External forces applied on the structure during 3D IC stacking can generate stress, leading to rupture, in the form of cracking or delamination, in the device. An experimental setup, provided by an industrial partner, was replicated in a FEM environment in order to simulate the effects of an external force acting on the open TSV. By comparing the simulations with measurement data two critical areas with high concentrations of mechanical stress were identified; one located above the applied external force and the other at the bottom corner of the TSV. In these areas different material layers are stacked and a high concentration of mechanical stress can generate mechanical failure such as cracking or delamination. The chosen approach is useful to identify a TSV geometry (re-enforcement materials and layer thicknesses), necessary to improve the mechanical stability of the structure.

The identified critical areas serve as potential candidates for delamination and were investigated in further detail. The critical conditions necessary for delamination propagation at the high stress locations were predicted. The critical locations are situated at the material interfaces, found in the multilayer structure at the bottom of the TSV. The delamination propagation was determined by calculating the energy release rate at the interfaces. Critical energy release rates for those interfaces are used as a criterion for the delamination propagation. The energy release rates have been calculated using FEM in combination with two different methods. For the first method the energy release rate is calculated using the J-Integral approach. For the second method the energy release rate is derived in two steps: in the first step the stress values of the FEM simulation at the interfaces between the materials are gathered, and in the second step the necessary parameters to calculate the energy release rate are fitted through regression analysis of the collected stress values. The first method has been applied to the interfaces present at the bottom of the TSV. The results have shown a critical instability at the SiO2/W interface. The highest energy release rate is found when the W layer was assumed to carry a high intrinsic tensile stress. The first method is realized by calculating an integral over the crack tip. However, if the considered material layers are very thin, as is the case in our study a suitable integral path around the delamination tip, with respect to the meshing density, can not be defined. Therefore the second method has been implemented and verified with data found in thin layer experiments. The two methods have been further employed to calculate the energy release rate for thicker layers in the same structure producing results with good agreement. These two methods can be used to investigate the critical factors which lead to delamination propagation.

When thin material films are stacked, as in TSVs, the mechanical stability of the system can be compromised by the presence of a high intrinsic stress. In the scope of this thesis a model for the simulation of the stress build-up during deposition of thin films was implemented by using FEM. Due to thermodynamical reasons, polycrystalline metal films deposited onto polycrystalline or amorphous substrates grow according to the Volmer-Weber mode. During the Volmer-Weber mode, three unique growth steps can be distinguished: nucleation, coalescence, and film thickening. In the two first steps the film stress evolves from compressive to tensile. In the third step, which is film thickening, the stress can return to compressive or stays tensile, depending on the continued grain-structure evolution during growth. Materials with a low adatom mobility (high melting temperature) exhibit a columnar grain structure which results in a constant stress during film thickening. For materials with a high adatom mobility (low melting temperature) the microstructure forms equiaxed grains which continue to evolve during film thickening, resulting in a possible compressive stress generation. Models were developed which are useful for the simulation of low and high adatom mobility materials. Stress behavior of low adatom mobility materials was analyzed during W growth onto a scalloped structure and onto a flat sample. Due to the deep reactive ion etching process a scalloped structure can form along the TSV sidewall. The simulation and measurement results have shown that the substrate shape influences the stress in thin films. Thin films grown on a scalloped surface, with a pronounced curvature, develop a small intrinsic stress. The scalloped geometry permits to reduce the film stress considerably. In addition, the implemented model was verified for high adatom mobility materials. The model is able to reproduce the measured data from two different experiments, where in the first Ag was deposited on a SiO2 layer and in the second Cu was deposited on a Au layer. For the first experimental results the effects of the deposition temperature on the film stress were replicated and for the second the effects of different growth rates were reproduced. High deposition temperatures and slow growth rates result in small intrinsic film stress. The implemented model for low adatom mobility materials can be applied to investigate the stress evolution in any geometry. The model for high adatom mobility can be used for the analysis of the fabrication effects in complex structures, such as metal deposition in open Cu-TSVs.

The aim of the simulations and models presented here help to understand the potential mechanical problems occurring during IC fabrication, while also enabling a physical prediction of the mechanical stability of open metal-lined TSVs. However, as the 3D integration technology evolves further studies and model improvements will be essential.

The employed methodology and the implemented model, which mimics external forces during the 3D stacking of ICs are used to analyze the stress behavior in the TSV structure. This simulation approach can be used to find alternative geometries and fabrication methods in order to limit the resulting mechanical failure in TSVs. This gives chip designers the possibility to reduce the necessity for expensive and time-consuming experimental tests. Nevertheless, the simulations can be further improved by considering the plastic behavior of the individual materials, but also of the entire multilayer structure. Stress-strain curves of thin films provide the necessary information to describe plasticity of a single material. However, the interaction between layers in a stacked structure can differ from the single layer material behavior. Further studies must be carried out to understand how the plasticity of the materials evolves inside the TSV structure.

The implemented model used to predict delamination has been implemented to investigate the factors which influence delamination. However, more experimental measurements of the critical energy release rate for interfaces which are present in the open TSV are necessary. Measurements of the SiO2/W interface have been performed by our industrial partner and they found that these results differ from those found in literature. The technique, the size of the samples, and the microstructure of the materials are all factors which influence the critical energy release rate. Therefore, new and different experimental methods to measure the critical energy release rate in open TSVs are essential.

The developed method used to simulate stress build-up in thin films has provided interesting results, in particular about deposition on scalloped substrates. Films grown on a scalloped structure develop less stress compared to a flat alternative. Stress measurements during film growth on different scalloped substrate geometries (different heights and widths of the scallops) should be performed to compare and validate the obtained results against measurements. The model for low adatom mobility materials is suitable to analyze the stress evolution in the IC fabrication processes.