3.2.3 Parasitic $npn$ and $pnp$ Transistors in Smart Power ICs

Figure 3.10 shows the schematic structure of parasitic $npn$ and $pnp$ transistors in LDMOSFETs. When an inductive load is switched by LDMOSFETs, the potential of the drain ($n^+$ at the low-side switch in the figure) can dive below the ground potential of $p$-substrate. Under this condition a considerable amount of electrons is injected into the substrate. These electrons either recombine with holes in the substrate or they are collected by another $n$-well of LDMOSFETs or logic CMOS. The substrate doping concentration and minority carrier lifetime in this region play a major role in the behavior of this parasitic $npn$-structure. With a high doping concentration and shorter minority carrier lifetime of the substrate, the parasitic $npn$-structure is suppressed significantly.

At the same time the potential of a source of the high-side switch ($n^+$ in the $p$-body) can be over supply voltage, and the $p$-body contact at the source side injects holes into the $n$-well. Most of these holes recombine in the $n$-well with electrons, but some reach the substrate. If the $n$-well doping is increased, this parasitic $pnp$-transistor gain can be suppressed.

The electrons and holes injected into the substrate can cause the latch-up of LDMOSFETs themselves, or they are collected by an $n$-well of the CMOS structure and can induce latch-up [124]. With the SOI or deep trench isolation the substrate current of a smart power IC can be effectively suppressed.

Figure 3.10: Schematic structure of the parasitic $npn$ and $pnp$ transistors in LDMOSFETs.