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5.11.1 Variational Masks

  When analyzing the behavior of a semiconductor device as a function of its geometrical dimensions, e.g., the dependence of the threshold voltage and other characteristics of a MOS transistor on the gate length (short channel effects gif), all lithography steps have to be supplied with varying coordinate values. These variations are usually performed after the link between ECAD and TCAD has been severed, i.e., in a stand-alone fashion just generating appropriate values without using mask files. While this approach is acceptable when there exists only a loose link with the ECAD domain, is imposes severe limitations on the application of ECAD tools for checking the coordinates generated against constraints stemming from design rules or from the two-dimensional (mask) situation.

To couple ECAD and TCAD more tightly, and also to facilitate the feed-back process once optimum coordinates have been found for a geometrical optimization problem, the variations must already be applied at the layout stage. To this end, layout needs to be parameterized and subjected to modification for each design space point to analyze. Figure 5.11 shows the principal mechanism for deriving varying coordinate values from the layout. As the challenges that arise when parameterizing geometrical data are far from being trivial, active research has still to be done in this area.

 figure1554
Figure 5.11:   Generation of mask data from variational layout. Before data is used, geometrical checks can be run on the layout produced from the template.



Christoph Pichler
Thu Mar 13 14:30:47 MET 1997