5.8 Design consequences

According to (5.9), the common mode coupling of layout structures such as traces and power-planes to the enclosure cavity field can be reduced by a reduction of the trace to ground plane distance d, which is determined by the dielectric layer thickness of the PCB. In comparison with standard PCB layer stacks, HDI technology with ultra thin layers or thin outer layers of standard PCBs will reduce the common mode coupling and the electromagnetic emissions accordingly. However, impedances of high speed signal traces have to be preserved by trace width reduction when the layer thickness is reduced.
Since the common coupling depends only on the vertical currents, the EMC design has to concentrate on the vertical interconnects of EMC critical components and on the PCB. The coupling from components on the PCB can be reduced by the selection of packages with shorter vertical interconnects. For instance, if a flash memory IC with a fast clock input is available with a BGA or a QFP package, the BGA type should be selected. A different package has other package inductances and capacitances. Thus, a signal integrity analysis is necessary when another package type is selected. The current magnitude frequency spectrum on the IC pins should be obtained from the transient signal integrity analysis by FFT. The current spectrum together with the reduced coupling factor from the changed package provide quantitative information about the achievable reduction of the emission level. A ground plane area on the outer PCB layer directly under the IC, as depicted in Figure 5.12, reduces the height of the package loop d compared to a PCB layout with a ground plane only in an inner layer. Although the distance of the enclosure cover to the PCB ground h is also reduced by raising the ground by the distance d, d/h is effectively reduced, because
h >> d(d-Dd)/(h-Dd) < d/h. Therefore, the ground should be routed directly under the IC and this ground has to be connected to the global PCB ground plane by vias, at least in the positions of the fast signal pins to enable the short current return path, depicted in Figure 5.13(a). A current loop on an IC is not generally the shortest, with the lowest inductance, because high resistive tracks on the die can lead to a lower overall loop impedance of extended loops. In particular, to reduce the magnetic coupling from the IC, the magnetic loop is effectively reduced by a ground plane under the package.

C. Poschalko: The Simulation of Emission from Printed Circuit Boards under a Metallic Cover