The structuring element suited to model such a process is a line, which represents an extreme case of an ellipsoidal. When the main axis is given by the etch or deposition rate and the minor axis by the cell resolution the line can be considered as degenerated ellipsoidal.
Fig. 3.12 shows on its left hand side an isolated linear structuring element. For this example the incidence direction of the particles is tilted by 30, which immediately gives a hint to an additional requirement for such a highly directional step, namely, testing of the visibility.
Depending on the incidence direction of the particles and the stability of the resist with respect to the impinging particles those parts of the substrate which are located in close vicinity to the mask edges are protected from the attack by the reactive particles. This effect is shown on the right hand side of Fig. 3.12. Just left from the right mask edge the part of the silicon surface located in the shadow from the mask is not etched.
As for the isotropic and anisotropic cases, the unidirectional modeling is completed with the corresponding deposition example. For the deposition example a vertical direction of the particle incidence is assumed, as can be seen with the isolated linear structuring element on the left hand side of Fig. 3.13. The assumption of strictly vertical particle incidence completely inhibits film deposition at the sidewalls of the mask opening.
To conclude the chapter about geometry editing with solid modeling and basic topography models, it has to be mentioned that up to this level, all operations for the definition of patterns have required interactive specification of the primitives in order to compose the desired geometries. It was the responsibility of the user to find a way how to compose more complex structures by the available primitives and process step emulations. It is clear that this is not the way, how devices are fabricated in a foundry. In order to process the wafers, manufacturing makes use of process recipes and chip designs coded in layout files. The transfer of the layout patterns onto the wafer is accomplished by means of lithography techniques. The optical principles building the fundamentals for the lithographic pattern transfer lead to deviations between the geometry defined in the layout and the patterns finally appearing on the wafer.
All these considerations lead to the conclusion that it is absolutely necessary to directly include the geometric information stored in the layout files into the solid modeling operations. Preferably the method for using the layout information should include lithography tools as well. How this link to layout and lithography is accomplished for the presented cellular solid modeling tool will be the topic of the next chapter.
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