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4. Inclusion of Layout and Lithography Simulation

Layout definition and lithography techniques are the crucial topics for the definition of the function of the chip and the transfer of the two-dimensional operational design to three-dimensional structures appearing on the wafer. The physical masking function is taken over by layers of photo-resists which are structured by projecting the chromium patterns of the reticles onto the wafer. The projection is realized by means of a photo-lithographic exposure step with subsequent development of the photo-active layer. For each process step in chip manufacturing, the masks define which areas on the substrate shall be exposed to a process and which shall be protected from its impact. Examples for these selectively applied processes are ion implantation which defines the doping distribution and thus the electrical behavior of the devices, oxidation for the formation of gate oxides and isolating oxide layers, and etching which is used for the definition of trenches, capacitors, spacers, contacts, vias, and metal lines.

Simulating the same lithography techniques as applied in manufacturing is highly desirable for the generation of the three-dimensional solid models. The fact that creating three-dimensional structures gets very quickly confusing and error-prone when creation means to edit hierarchical point and reference lists forming polygons and segments is only one argument for the direct utilization of layout information. Editing becomes easier when assisted by graphical user interfaces (GUIs), still, maintaining the consistency of the geometries and assuring correct connectivities at interfaces is a painful job. Automatic generation of the structures by combining the patterns already defined in the layout with the process recipe is the ideal solution which guarantees consistent three-dimensional geometries. At this point high level physical modeling has to be balanced carefully against fast and sufficiently accurate solid modeling.

Optical lithography represents a process step which is similarly complex to oxidation or CMP. Rigorous simulation of optical lithography must include aerial image formation considering the complete optical pathway of the projection system and the transfer of the aerial image into the photo-active layer by means of exposure simulation, as well as the evolution of the final resist profile by means of development simulation and resist etching.

Rigorous lithography simulation is of great importance. As already mentioned in the introduction, lithography is the decisive factor for reducing the smallest feature size of the devices and worth to be investigated separately. The etching simulation presented in this thesis is well suited to complete such a rigorous lithography simulation with accurate development modeling. The details of this application will be presented in Chapter 5. Within the scope of solid modeling it has to be checked, whether a comprehensive simulation of exposure and development is really necessary or only a waste of valuable simulation time.

As an alternative it might be interesting to take a look at the illumination system and to check whether a simulation restricted to aerial image formation turns out to be sufficient. The aerial image represents the projection of the exposed polygons from a specific layer from the layout file appearing on the wafer surface. Assuming that this pattern is transfered exactly vertically downwards into the substrate and neglecting reflection and standing wave effects, aerial image simulation might be sufficient to check the printability of the layout and to examine line narrowing and line shortening effects.

How layout and lithography are coupled with the presented solid modeling approach will be shown in this chapter. Section 4.1 demonstrates how simple layouts may be defined with an interactive layout editor and how the thus generated layers may be used instead of the combined geometric primitives presented in the previous chapter. The application of this approach will be demonstrated by means of two examples where the method is used for the generation of the solid model of a DRAM cell and a two metal layer interconnect structure (Section 4.1.1). Section 4.2 highlights some aspects of aerial image formation investigated by lithography simulation and its influence on interconnect line formation and electrical characterization (Section 4.2.1).

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W. Pyka: Feature Scale Modeling for Etching and Deposition Processes in Semiconductor Manufacturing