6.4 Optimization Criteria and Results

Primarily two kinds of parameters could be optimized: speed and energy efficiency. But which definition of speed should be used, or does this matter at all? And which criterion for energy efficiency yields the best tradeoff between energy efficiency and speed?

Figures 6.6-6.15 show the resulting optimum values as functions of the gate length. The curve parameter is the optimization criterion. When the value plotted is present in the set of optimization criteria the respective curve is plotted with a thicker line.

For speed optimization five different criteria were used:

1.

minimize

2.

minimize

3.

minimize

4.

maximize

5.

maximize $\ensuremath{V_{\mathit{DD}}}\xspace -\ensuremath{V_{\mathit{T}}}\xspace$

The traditional criteria are to maximize or to minimize on the design side the available ``voltage drive'' $\ensuremath{V_{\mathit{DD}}}\xspace -\ensuremath{V_{\mathit{T}}}\xspace$ (and thereby) is kept a large as possible. Despite the fact that an increase of usually also improves the performance it turns out that using the on-state current as an optimization criterion does not yield optimal delay times, especially, when the capacitive loading is small ( ) (Figs. 6.6 and 6.7). The optima found with and $\ensuremath{V_{\mathit{DD}}}\xspace -\ensuremath{V_{\mathit{T}}}\xspace$ as a criterion obviously violate some criterion, so that the acceptable devices with maximum lie closer to the ones with minimum and , which may be accidental (Figs. 6.8 and 6.9). Minimizing the CV/I delay metric , on the other hand, would foster about 50% larger real delay times when the interconnect capacitance is larger ( ). The reason is that minimizing also minimizes the gate capacitance per area, which decreases the available (cf. Fig. 6.11).

Figure 6.6: Optimal unloaded-inverter delay obtained by unconstrained optimization with various delay criteria

Figure 6.7: Optimal inverter delay obtained by unconstrained optimization with various delay criteria

Figure 6.8: Optimal unloaded-inverter delay obtained by constrained optimization with various delay criteria

Figure 6.9: Optimal inverter delay obtained by constrained optimization with various delay criteria

Figure 6.10: Optimal CV/I delay obtained by constrained optimization with various delay criteria

Figure 6.11: Optimal drive current obtained by constrained optimization with various delay criteria

For the optimization of energy efficiency the following criteria were applied to the data

1.

minimize

2.

minimize $\ensuremath{E_{\mathit{s}}}\xspace \ensuremath{t_{\mathit{d}}}\xspace$

3.

minimize $\ensuremath{E_{\mathit{s}}}\xspace (\ensuremath{t_{\mathit{d}}}\xspace =2{\ensuremath{t_{\mathit{d}}}\xspace }_{\mathit{,min}})$

4.

minimize $\ensuremath{t_{\mathit{d}}}\xspace (\ensuremath{E_{\mathit{s}}}\xspace =2{\ensuremath{E_{\mathit{s}}}\xspace }_{\mathit{,min}})$

and the key results are shown in Figs. 6.12-6.15. Taking just as a criterion leads to very slow devices at only a small improvement of the energy efficiency obtained by minimizing $\ensuremath{E_{\mathit{s}}}\xspace \ensuremath{t_{\mathit{d}}}\xspace$. For high-performance technologies the best way seems to be to minimize the switching energy with a prescribed delay time, which is proportional to the minimum (Figs. 6.13 and 6.14). At $\ensuremath{t_{\mathit{d}}}\xspace =2{\ensuremath{t_{\mathit{d}}}\xspace }_{\mathit{,min}}$ the energy efficiency can still be improved by a factor of 10 in comparison to the minimum- case. Furthermore, the devices can operate at much lower currents and voltages (see Figs. 6.15 and 6.16)

Figure 6.12: Optimal unloaded-inverter obtained by constrained optimization with various energy criteria

Figure 6.13: Optimal inverter delay obtained by constrained optimization with various energy criteria

Figure 6.14: Optimal switching energy obtained by constrained optimization with various energy criteria

Figure 6.15: Optimal drive current obtained by constrained optimization with various energy criteria

Figure 6.16: Optimal supply voltage obtained by constrained optimization with various energy criteria

Figure 6.17: Optimal linear threshold voltage obtained by constrained optimization with various energy criteria