6.2.2 Infinite Inverter Chain Emulation

Fig. 6.3 also shows how the data container is embedded into the evaluation network. The post-processing step not only evaluates the data necessary for the target and constraint evaluation, it also prepares the simulation results for storage in the data container. The output V-t curves are shifted by the actual delay times so that they can be used as input V-t curves for subsequent steps. The input C-V curves are calculated from the input I-t curves using (6.1) and stored in the data container for usage as load C-V curves, accordingly.

Fig. 6.4 shows the time-shift method used to derive the new input V-t curve $V_{\mathrm{in,new}}(t)$ for the on-transition: The output V-t curve of an off-transition simulation $V_{\mathrm{out}}(t)$ is shifted to the left by the inverter delay time $t_{\mathrm d}$ of this transition providing the new input V-t curve. The corresponding input V-t curve $V_{\mathrm{in}}(t)$ for the off-transition is also shown. This method guarantees that, during optimization, the delay of the input V-t curve ( $t_{\mathrm d,in}$ in this figure) stays constant.

Figure 6.4: The time-shift method used to obtain the inverter input V-t curve from the output V-t curve of the previous step.

Due to the capacitive coupling between the input and output nodes of the inverter stage, there is a slight overshoot of the output voltage at the beginning of a transition, as can be seen in Fig. 6.4. When the input voltage starts to rise, the capacitive coupling makes the output voltage increase, too, until the input voltage is high enough to switch the inverter stage.

For simulation purposes this overshoot is neglected in the time-shift method. If the overshoot were considered the input V-t curves would not be monotonous which means that there would not exist a unique C-V curve for the load capacitance $C_\mathrm{L}$. However, the initial input voltage has to be either $V_{\mathrm{dd}}$ or 0 V for the on- or off-transition, respectively, so that the leakage current can be extracted properly.

Tailoring the overshoot is accomplished by introducing a lower and upper boundary, 0 V and $V_{\mathrm{dd}}$, respectively, for the input voltage. When evaluating the function for the voltage dependent load capacitance (6.1), any arguments which lie outside the range of 0 V to $V_{\mathrm{dd}}$ are set to either 0 V or $V_{\mathrm{dd}}$ since (6.1) is only defined within this range.

Fig. 6.5 shows the optimization sequence illustrating when new data is stored in the data container. Any time a temporary minimum is found after a number of evaluation steps, the new input V-t and load C-V curves are processed and the results are stored in a wait-state. After the gradient calculations are finished, these data are transferred into the data container. The wait-state is necessary because the gradients have to be calculated still using the old data, therefore the container data refresh takes place just before the first evaluation step which is immediately after the gradient calculations.

Figure 6.5: The optimization sequence for gate delay time optimizations.

This permanent update of the input V-t and load C-V curves provides a self-contained emulation of an infinite inverter chain. At the time when the optimization procedure converges, the input and output curves of the inverter will be self-consistent meaning that the inverter behaves exactly like one stage of a ring oscillator.

To provide a good initial guess for the device simulations during subsequent optimization steps the output PIF files of both simulations are saved. This is done after each evaluation step shown in Fig. 6.5. The output PIF files from the gradient steps are dropped away because the results are very close to the previous evaluation step, anyway.