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5.3 Case Study: Simulation of Breakdown and Snap-Back

In this case study a smart power test structure from Infineon Technologies is analyzed. This structure is used for switching purposes in automotive applications. It shows that electronic equipment has to cope with very harsh conditions in these environments [216,113]. Hence, semiconductor devices have to withstand ambient temperatures of as low as $ -40$ $ ^{\circ}$ C. On the other hand, in the drivers interior temperatures can raise to up to $ +85$ $ ^{\circ}$ C, under the hood up to $ +125$ $ ^{\circ}$ C, and for the devices mounted on the engine temperatures can reach $ +150$ $ ^{\circ}$ C[216,113]. Not only the temperature, but also electrical harsh conditions are typical for vehicles. The power supply, the grounding, and voltage levels on signal lines experience high disturbances. These high energetic interfering signals can lead to voltage pulses increasing the nominal supply voltage up to 5 times [216]. Electronic devices in automotive environments have therefore be rated of up to 70 V, although the power lane is nominally 14 V.

5.3.1 Specifications

The structure that is analyzed in this study is basically a vertical smart DMOS with an architecture similar to the one shown in Fig. 2.10. The device demonstrated random failures during operation. It was suspected that voltage peaks lead to breakdown and further to the snap-back state (compare Section 3.2.4). Therefore, the responsible parasitic n-p-n bipolar structure was measured using the TLP (transmission line pulse) method [217]. A snap-back characteristic with a holding voltage of approximately 10 V was observed. This holding voltage lies below the supply bias of 14 V. Therefore, the device remains in snap-back state and the resulting high current does not decay. Eventually, this leads to the destruction of the device due to overheating.

The idea is to investigate the influence of the doping profile on the holding voltage using device simulation. To accomplish this, the first necessary step is to reproduce the experimental snap-back characteristics. Especially the holding voltage has to show good agreement. As the next step, a structure which is similar to the first one should be analyzed and optimized. Unfortunately, no measurement data are provided for this second device.

Simplified versions of the devices are used for the simulations. They basically consist of an n-doped EPI layer on top of an n$ ^+$ backside doping. An implanted p-well extends across the whole simulation domain. Finally an n$ ^+$ implant and a contact are placed in the right upper corner. The device is sketched in Fig. 5.7. The first structure is generated using one-dimensional measured SIMS-profiles of the different dopants incorporated into the device. The profiles represent vertical cuts through different regions. For the second structure, some of the SIMS-profiles were exchanged by those obtained from process simulation. Also the vertical extension was increased. All doping profiles and contacts which are not relevant for the simulation have been omitted. Additionally, the structures are assumed to be symmetric. Both basically act as a vertical parasitic n-p-n bipolar transistor. The emitter contact is on the top surface and the collector contact is at the backside. The p-well acts as the base region. It is not connected and therefore remains floating.

Figure 5.7: Sketch of the simplified smart power device with n$ ^+$ backside, n-EPI, p-well and n$ ^+$ emitter contact. The collector is at the bottom of the device.

To model the characteristics of these structures, the device simulator MINIMOS-NT is used. The large dimensions of the device suggest to employ the drift-diffusion framework. The probably most important physical mechanism responsible for the breakdown and snap-back effect is the impact-ionization generation. For proper modeling of the impact-ionization rates, the extended Chynoweth relation is used as presented in (5.13).

5.3.2 The Snap-Back Curve

First the snap-back simulation is performed using a voltage boundary condition. The collector voltage is increased starting from 0 V up to the breakdown voltage. From there on, a current boundary condition is used. This method gives the possibility to trace the whole snap-back curve. Fig. 5.8 demonstrates the simulation results against the measurement data. For a better orientation along the snap-back curve, the points I-IV have been marked in Fig. 5.8(b). The distributed values of the II rate and the electron density at those positions are shown in Fig. 5.9 and Fig. 5.10, respectively.

Figure 5.8: The snap-back characteristics of the test structure using linear (a) and logarithmic (b) scale. In the right plot, the markers I-IV which are used in the text are shown.
(a) Snap-Back Curve (lin)

(b) Snap-Back Curve (log)

Figure 5.9: Impact-ionization generation rate at different positions in the snap-back curve (a)-(e); for the position marks I-IV see Fig. 5.8(b). The electron concentration along the cutline is shown in (f).

Figure 5.10: Electron concentration at different positions in the snap-back curve (a)-(e); for the position marks I-IV see Fig. 5.8(b). The electron concentration along the cutline is shown in (f).

Until the device breakdown (point I), only the small cut-off current can be observed. The electric field in the device peaks at the base-collector junction and increases with the collector voltage. Due to the increasing field the impact-ionization generation becomes more pronounced. Eventually, the avalanche breakdown occurs at the point I.

Continuing to the point II, the further increase of current is related to an intensified impact-ionization generation. The rapidly growing concentration of carriers generated in the gate region makes it possible to carry higher currents at lower collector voltages. This explains the negative differential resistivity in this area. Additionally, the electrostatic potential in the base region increases. This leads to a forward bias across the base emitter region and turns on the n-p-n transistor. Therefore, additional electrons are injected into the base region [109,218].

Between the points II and III, the concentration of electrons in the base region begins to exceed the acceptor concentration. Consequently, the mobile charge density becomes higher than the fixed charge density [109,218] and the metallurgical junctions are therefore not valid anymore. Hence, the effective base-collector junction is pushed towards the n-n$ ^+$ junction between the EPI layer and the backside doping. This effect is called ``base push-out'' or ``Kirk effect'' [32] and evolves around the snap-back voltage at the point III. Together with the base push-out, also the peak electric field and the impact-ionization are moved deeper into the silicon.

Finally, the peak electric field reaches the backside of the structure. The higher doping concentration in this region yields a higher impact-ionization generation. Additionally, the current path through the device becomes broader. This finally leads to the voltage drop down to the holding voltage in point IV. Here, the generated carriers flood the whole device. At this state, no stationary operation would be possible. The high current densities lead to a rapid temperature increase and the device would be destroyed very quickly. However, with TLP measurements, these operating points can still be observed. Although no self-heating is employed in this simulation, the calculated holding voltage agrees well with the measurement data.

5.3.3 Structure Variations

To investigate the influence of the doping profile on the snap-back curve further simulations have been performed. For this purpose, the structure is modified using doping profiles achieved from process simulations. The structure is extended further into the depth of the device, i.e., the direction towards the backside of the device. These modifications of the structure already show a higher holding voltage of approximately $ 20 $ V. For the further optimization of the holding voltage, the general requirements to the device architecture have to be considered. Therefore, only a few properties of the doping profile are allowed to be changed. To avoid any influence on the devices embedded in the process, the upper layers, i.e., the emitter and the base area, should remain unchanged. Also the doping concentrations of the EPI layer and the backside must be kept at the same level. This gave rise to the two possible variations, both concerning the n-n$ ^+$ junction. First, the depth of the junction can be varied, i.e. changing the thickness of the EPI layer. Also a variation of the junction steepness can be employed (see insets in Fig. 5.11).

Figure 5.11: Holding (a) and snap-back voltage (b) in dependence on the backside doping. The upper inset symbolizes the variation of the backside doping in depth. The onset of the backside doping lies in the range of 11.5 to 15.5 µ m. The lower inset symbolizes the variation of the steepness. It is denoted by a ``stretching'' factor in the range of 1 to 4. The holding voltage in (a) strongly depends on the variation of the steepness, whereas a change of the depth has only minor impact. The snap-back voltage (b) especially depends on the depth of the backside doping. It also seems to be influenced by the steepness. However, this comes from the fact that a change of the steepness also changes the depth (compare lower inset).


The increase of the EPI thickness leads, as shown in Fig. 5.11(b), to a change of the snap-back voltage. Here (point III), the evolving base push-out effect dominates the device behavior. A thicker EPI layer can withstand a higher voltage at approximately the same electric field. Therefore, the shift of the effective base-collector junction towards the backside doping occurs at higher voltages. This correlates to observations in [109]. Once the base push-out saturates, no differences in the device behavior can be observed. The holding voltage therefore remains unchanged.

The second variation which was investigated concerns the steepness of the backside doping. For the simulation study the profile was changed artificially (see inset in Fig. 5.11). The results are shown in Fig. 5.11(a). At the holding voltage the device is dominated by the high impact-ionization rate at the n-n$ ^+$ junction. By flattening the junction, lower maximum fields and therefore lower impact-ionization rates can be expected. This tendency correlates with simulation the results, which show an increase of the holding voltage for a flattened profile. Note that the steepness variations also changed the EPI thickness in this setup. This explains the influence of the steepness on the snap-back voltage.

5.3.4 Simulation Difficulties

Snap-back simulations often cannot be performed straight-forwardly with TCAD tools. The initial part, the voltage stepping up to the breakdown voltage, is a standard use-case of device simulations. Until this point, commonly no problems are faced. However, going beyond the breakdown gives rise to one or more of the following difficulties:

The snap-back simulations often lead to bad convergency of the Newton iteration scheme [218]. To overcome this, small voltage and/or current stepping is required. In addition, a good mesh optimized for the snap-back simulation improves the overall convergence. This is especially true, due high local variations in the carrier concentrations, for example. Also effects like the base push-out mechanism have to be considered for the mesh generation. Additional discussions on numerical issues related to the simulation of impact-ionization phenomena and especially on problems encountered for high-voltage devices are found in Section 7.4.

5.3.5 Discussion

The reference simulation shows qualitatively good agreement as compared to the measurement data. Note that these results are obtained without performing extra calibrations. This means that even better results can be expected by performing a proper model calibration. This suggests that for this structure, the static iso-thermal simulations are sufficient for a proper description of the problem. However, other investigators claim that estimations without self-heating are not valid for snap-back modeling, which was especially observed in lateral devices [221]. Reconciling of this contradiction is the subject of the further research. For this purpose, three-dimensional device simulations have to be performed in order to capture the self-heating effects. However, such simulations should not be related to conceptual difficulties because MINIMOS-NT is capable for three-dimensional device modeling and incorporates the self-heating.

next up previous contents
Next: 6. Hot-Carrier Reliability Modeling Up: 5. Impact-Ionization Generation Previous: 5.2 Modeling Approaches

O. Triebl: Reliability Issues in High-Voltage Semiconductor Devices