2.3.2 Barrier and Capping Layers

Several approaches, relying on additional layers introduced under the gate, have also been proposed. The first was by Hu et al. [52], who suggested a pn-junction under the gate. Mizutani et al. [18] proposed an InGaN capping (cap) layer in order to raise the conduction band under the gate. Also Higashiwaki et al. [53] reported an AlN/GaN structure with a thin AlN layer, with positive $ V_\ensuremath {\mathrm {th}}$.

Figure 2.2: $ g_\ensuremath {\mathrm {m}}$ vs. $ V_\ensuremath {\mathrm {th}}$ of GaN HEMTs featuring different techniques.

Fig. 2.2 shows the correlation between $ V_\ensuremath {\mathrm {th}}$ and $ g_\ensuremath {\mathrm {m}}$ achieved with the different techniques. During the years an overall significant improvement can be noted. The last results show that for the AlGaN/GaN system there is a certain limit which, while allowing for trade-off between Vth and $ g_\ensuremath {\mathrm {m}}$, has to be overcome. Table 2.2 gives a summary of the advantages and the drawbacks of the different approaches.

Table 2.2: Comparison of different techniques for E-mode structures.
Technique Advantages Disadvantages Reported by
gate recess on-wafer surface damage,
not self-centered
HRL [42,43], UIUC [17,46],
Oki [45], UCSB [49]
surface treatment low access resistance,
no 100% damage-recovery HKU [16,54,48],
UCSB [49]
InGaN cap good RF performance low $ g_\ensuremath {\mathrm {m}}$& $ I_\ensuremath{\mathrm{dMAX}}$ Univ. Nagoya [18]
AlN/GaN good DC performance low 2DEG mobility Fujitsu [53]
pn-junction gate on-wafer (selective) very low $ I_\ensuremath {\mathrm {D}}$ and $ g_\ensuremath {\mathrm {m}}$ USC [52]
thin barrier low gate leakage high R $ _\ensuremath{\mathrm{on}}$ Furukawa [50], Nichia[51]

S. Vitanov: Simulation of High Electron Mobility Transistors