Several approaches, relying on additional layers introduced under the gate, have also been proposed. The first was by Hu et al. , who suggested a pn-junction under the gate. Mizutani et al.  proposed an InGaN capping (cap) layer in order to raise the conduction band under the gate. Also Higashiwaki et al.  reported an AlN/GaN structure with a thin AlN layer, with positive .
Fig. 2.2 shows the correlation between and achieved with the different techniques. During the years an overall significant improvement can be noted. The last results show that for the AlGaN/GaN system there is a certain limit which, while allowing for trade-off between Vth and , has to be overcome. Table 2.2 gives a summary of the advantages and the drawbacks of the different approaches.
|gate recess||on-wafer||surface damage,
|HRL [42,43], UIUC [17,46],
Oki , UCSB 
|surface treatment||low access resistance,
|no 100% damage-recovery||HKU
|InGaN cap||good RF performance||low &||Univ. Nagoya |
|AlN/GaN||good DC performance||low 2DEG mobility||Fujitsu |
|pn-junction gate||on-wafer (selective)||very low and||USC |
|thin barrier||low gate leakage||high R||Furukawa , Nichia|