Subsections

• 3.4.1 Capacitance Matrix
• 3.4.2 Simulation Example

3.4 Extended Single-Mode AC Analysis

As already discussed above, by using the standard single-mode AC a general complex-valued amplitude can be applied to an arbitrary number of terminals of the device. However, under these circumstances the calculation and assembly of the complete admittance matrix is a cumbersome task. For that reason the simulator has been extended to provide a feature for the automatic calculation of the complete matrix.

The intrinsic scattering matrix $\underline{\ensuremath{\mathbf{S}}}$ can be calculated by the following analytical formula [244]:

$$\ensuremath{\underline{\ensuremath{\mathbf{S}}}} = 2 (\ensuremath... ...remath{\underline{\ensuremath{\mathbf{Y}}}})^{-1} - \ensuremath{\mathbf{I}} \ ,$$ (3.20)

where $\ensuremath{\mathbf{I}}$ is the identity matrix and $\underline{\ensuremath{\mathbf{Y}}}$ the intrinsic admittance matrix. In order to obtain the usually applied formulae for a two-port network (see Appendix D), the following calculation can be performed:

$$\ensuremath{\underline{\ensuremath{\mathbf{A}}}} = \ensuremath{\m... ...nderline{Y_{21}}} & 1 + \ensuremath{\underline{Y_{22}}} \end{array} \right) \ ,$$ (3.21)

$$\ensuremath{\underline{\ensuremath{\mathbf{A}}}}^{-1} = \frac{1}{... ...{21}}} & \phantom{-}1 + \ensuremath{\underline{Y_{11}}} \end{array} \right) \ ,$$ (3.22)

with

$$\ensuremath{\underline{D_\mathrm{S}}} = (1 + \ensuremath{\underli... ...{Y_{22}}}) - \ensuremath{\underline{Y_{12}}} \ensuremath{\underline{Y_{21}}}\ .$$ (3.23)

After multiplying by two and deducting the identity matrix, the following well-known formulae can be derived:

$$\ensuremath{\underline{S_{11}}} = \Bigl((1 - \ensuremath{\underli... ...ensuremath{\underline{Y_{21}}}\Bigr) / \ensuremath{\underline{D_\mathrm{S}}}\ ,$$ (3.24)

$$\ensuremath{\underline{S_{12}}} = (-2 \ensuremath{\underline{Y_{12}}}) / \ensuremath{\underline{D_\mathrm{S}}} \ ,$$ (3.25)

$$\ensuremath{\underline{S_{21}}} = (-2 \ensuremath{\underline{Y_{21}}}) / \ensuremath{\underline{D_\mathrm{S}}} \ ,$$ (3.26)

$$\ensuremath{\underline{S_{22}}} = \Bigl((1 + \ensuremath{\underli... ...ensuremath{\underline{Y_{21}}}\Bigr) / \ensuremath{\underline{D_\mathrm{S}}}\ .$$ (3.27)

3.4.1 Capacitance Matrix

The capacitances are calculated according to the charge-based capacitance model [9]: the terminal charges are in general a function of the terminal voltages. Each terminal has a capacitance with respect to the remaining terminals. For that reason a four terminal device has 16 capacitances.

All capacitances form the so-called indefinite admittance matrix. Each element $C_{ij}$ of this matrix describes the dependence of the charge at the terminal $i$ with respect to the voltage applied at the terminal $j$ with all other voltages held constant. In general,

$$C_{ij} = \left\{ \begin{array}{rl} \displaystyle-\frac{\partial Q... ...displaystyle \frac{\partial Q_i} {\partial V_j}, & i = j\ . \end{array} \right.$$ (3.28)

The signs are chosen to keep the capacitances positive for all devices for which the node charge is directly proportional to the voltage at the same node, but indirectly proportional to the voltage of any other node. Thus, for a four terminal MOS transistor the 16 capacitances of the matrix $C_{ij}$ are defined as follows:

$$C_{ij} = \left[ \begin{array}{rrrr} C_\mathrm{GG} & -C_\mathrm{GD... ...rm{BG} & -C_\mathrm{BD} & -C_\mathrm{BS} & C_\mathrm{BB} \end{array} \right]\ .$$ (3.29)

Each row and column sum must be zero in order to fulfill Kirchhoff's laws. For that reason, the capacitances are not independent from each other, but one of the four can be calculated with the remaining three. The gate capacitance $C_\mathrm{GG}$ is therefore:

$$C_\mathrm{GG} = C_\mathrm{GS} + C_\mathrm{GD} + C_\mathrm{GB}\ .$$ (3.30)

The four capacitances $C_\mathrm{GG}$, $C_\mathrm{GG}$, $C_\mathrm{GG}$, and $C_\mathrm{GG}$ are the self-capacitances of a MOS transistor, whereas the remaining twelve are the internodal, intrinsic, or trans-capacitances. They are non-reciprocal and the corresponding capacitances differ both in value and physical interpretation [9].

3.4.2 Simulation Example

The extended small-signal features have been evaluated by a comparison with results of the commercial simulator DESSIS [111]. The structure, which has been designed with the program MDRAW, was converted by using ISE2PIF and is shown in Figure 3.11. For $f = 100\,$MHz, $\ensuremath{V_\mathrm{GS}}= 0.0\,V$, and $\ensuremath{V_\mathrm{DS}}= 0.0\,V$ the simulator calculates the admittance matrix shown in Table 3.1.

Figure 3.11: Part of the investigated device structure with a depth of 1$\ \mu$m.

Table 3.1: Admittance matrix calculated by MINIMOS-NT for a frequency $f = 100\$MHz and terminal voltages $\ensuremath{V_\mathrm{GS}}= 0.0\,V$ and $\ensuremath{V_\mathrm{DS}}= 0.0\,V$.

	Gate		Drain		Source		Bulk		$\sum$
	Re	Im	Re	Im	Re	Im	Re	Im	Re	Im
Gate	2.2e-11	2.9e-07	4.2e-11	-9.6e-08	4.2e-11	-9.6e-08	-1.0e-10	-1.0e-07	-1.5e-19	9.2e-18
Drain	4.2e-11	-9.6e-08	2.0e-10	5.5e-07	1.2e-10	-1.0e-10	-3.7e-10	-4.5e-07	-1.2e-14	-1.2e-16
Source	4.2e-11	-9.6e-08	1.2e-10	-1.0e-10	2.0e-10	5.5e-07	-3.7e-10	-4.5e-07	-1.4e-15	-2.8e-15
Bulk	-1.0e-10	-1.0e-07	-3.7e-10	-4.5e-07	-3.7e-10	-4.5e-07	8.5e-10	1.0e-06	-7.0e-17	5.3e-17
$\sum$	1.8e-17	1.3e-19	-1.2e-14	-7.2e-17	-1.4e-15	-2.8e-15	-7.2e-17	9.5e-18

The last row of Table 3.1 contains the column sums, and the last column the row sums. Due to numerical reasons, zero can hardly be obtained, but the error is significantly lower than the entries in the matrix. After the calculation of the steady-state operating point, the solution of the complex-valued linear equation system requires 4.2$\,$s on a 2.4$\,$GHz Intel Pentium IV with 1$\,$GB memory running under Suse Linux 8.2. The dimensions of the complete and inner equation system are 6,610 and 4,805, respectively. In Figure 3.12, the gate drain capacitance $C_\mathrm{GD}$ as calculated by MINIMOS-NT is compared with results of DESSIS. Note, that the sign of the DESSIS result had to be inverted.

Figure 3.12: Gate drain capacitance versus gate voltage at $V_{\textrm {D}} = 0\ V$: comparison of simulation results of MINIMOS-NT and DESSIS.