The demand for constantly increasing computational power and memory space
is the force behind the miniaturization of integrated circuits, which took
place over the last thirty years and which will continue for the next
decades to come. Semiconductor product miniaturization is driven particularly
by DRAMs. They made a development from 1 Kbit chips in the early 1970s to
1 Gbit prototypes today. The corresponding reduction in
feature size was from 8 m for 1 Kbit chips to 0.18 m for 1 Gbit
chips. In order to sustain the progress miniaturization will be driven
further into the nanometer regime. Unfortunately conventional devices cannot
be scaled down straightforwardly. Many problems which are caused by
quantum mechanical effects arise, such as ballistic transport and oxide
tunneling. Also the interconnect issue becomes increasingly problematic at
increased integration densities.
Single-electronics offers solutions to some of the pressing problems which arise from advanced miniaturization. In contrast to conventional devices which experience a degradation in their device behavior when scaled to nanometer dimensions, single-electron devices show improved characteristics when their feature size is reduced. This improvement holds up to atomic dimensions. This difference in conventional and single-electron devices stems clearly from the fact, that single-electron devices are based on quantum mechanical effects which get more pronounced at smaller dimensions. Along with the superior scaling behavior comes a tremendous improvement in power consumption. Thus, energetically no restrictions exist to exploit the tremendous integration densities which are possible with devices only a few nanometers in size. Unfortunately the interconnect problem is not improved by single-electron devices and remains as a very important issue to be addressed for the successful implementation of integrated circuits with increased integration densities. A possible solution for the interconnect problem is a merely locally interconnected architecture.