2.2 Strained Interfaces

The end of scaling has often been predicted [48], but until now, always been proven wrong. For instance, end of scaling at $\sim400\,\mathrm{nm}$ due to the limit of spatial resolution by lithography [49,50] and at $3\,\mathrm{nm}$ oxide thickness as a result of increasing gate leakage current [51,52] has been predicted, but by brilliant engineers circumvented. Presently the physical scaling of the $Si$ gate oxide thickness has been halted [48] and the improvement through material properties became state of the art. As a result of the higher vertical fields (constant voltage scaling), in down scaled MOSFET devices, the mobility tends to lower values. Hence, at the $90\,\mathrm{nm}$ technology node strain techniques have been introduced [53,54].

First investigations of strain on the intrinsic mobility took place in the 1950's [55,56]. In the 1990's the concept of enhancing mobility with strain gained interest again [57]. Welser et al. [58,59] found a $70\%$ higher effective mobility $\mu_{\mathrm{eff}}$ compared to the value in unstrained substrate's. In the following years many different technologies to introduce strain into the channel of a MOSFET have been developed.

Strain techniques can be classified into two main categories. There are global strain techniques, where strain is introduced across the entire substrate, and local strain techniques, which insert strain locally at certain places. An overview of widespread strain technologies is depicted in Fig. 2.5. In the following chapter several common strain technologies are reviewed.

Figure 2.5: Overview of common strain techniques.