next up previous contents
Next: 2.3 Ferroelectric Gate Stacks Up: 2.2 Strained Interfaces Previous: 2.2.1 Global Strain


2.2.2 Local Strain

There are manifold processes that can be utilized to generate strain in the transistor channel (Fig. 2.5). The subsequently described techniques induce strain in the MOSFET channel locally and therefore are often adressed as local strain techniques.

Beginning in the late 1990's the influence of local stress induced by various process steps on the MOSFET performance was studied. The following process steps were identified to introduce stress into the transistor channel:

In spite of initially lower strain levels compared to global strain techniques, local strain techniques feature three main advantages:

A key issue is the optimization of process modules towards maximization of beneficial effects from stressors while minimizing negative side effects. A downside of process-induced strain techniques is their less predictable behavior at scaling due to their strong device geometry dependence[78].

The following chapters are devoted to four relevant stress-transfer techniques: CESL, Stress Memorization Technique (SMT), Selective Epitaxial Growth (SEG) of source and drain regions, and STI. Contact Etch Stop Liner - Gate Stacks

The contact etch stop liner technique (CESL) is realized after wafer silicidation by uniformly depositing a highly stressed liner on top of the gate stack. Dependent on the thickness and material properties of the liner different stress conditions are realized[74]. Yang et al. [79] showed an $ 11\,\%$ enhancement of the saturated drive current of n-channel and $ 20\,\%$ for p-channel MOSFETs. Applying one single liner limits to one type of stress for n-channel and p-channel MOSFETS. Accordingly, only the mobility of one transistor type is enhanced, while the other eventually is deteriorated, similar to global strain techniques. As a consequence, two types of stress liners have to be introduced, in order to improve the performance of n-channel and p-channel MOSFETs. This is implemented by a Dual Stress Liner (DSL) process with a highly tensile nitride deposited on top of the n-channel MOSFET gate stack, while a highly compressive nitride is deposited on top of the p-channel MOSFETs gate stack[79,80].

More than $ 2.0\,\mathrm{GPa}$ tensile and $ 2.5\,\mathrm{GPa}$ compressive stress have been shown for $ Si_{3}N_{4}$layers. This correlates to a stress level of more than $ 1\,\mathrm{GPa}$ in the MOSFET channel [81] and competes in magnitude with the stress induced by selective epitaxial growth ( Stress Memorization Gate Stack

For this technique, first a tensile stressor capping layer is deposited and then a spike anneal for dopant activation is performed [76,82,83,84]. Regardless of removing the stressor nitride layer before the silicide process, the stress is transferred from the nitride to the channel during annealing. The stress memorization takes place via re-crystallization of source, drain, and the poly gate amorphized layer. Up to $ 15\,\%$ on-current enhancement for n-channel MOSFETs is achieved by this technique[85]. Selective Epitaxial Growth

Selective growth of a local epitaxial film in the source and drain regions of a transistor is able to introduce uniaxial strain in the channel. Arising from the mismatch in lattice constants between source/drain regions and the channel region, one is able to generate large uniaxial stress. This is accomplished by etching the source and drain regions and forming recess areas. Then, these pockets are filled with epitaxy.

However, it is also possible to grow the epitaxial film directly on top of source and drain without etching these regions in advance[86]. Depending on the lattice constant mismatch and epitaxial layer thickness the induced stress varies. For instance, in order to create uniaxial compressive stress in p-channel MOSFETs epitaxially grown $ SiGe$ is used [78,87,88], while tensile stress in n-channel MOSFETs can be achieved via $ Si_{1-x}C_{x}$ stressors with a molefraction of $ \sim 1\%$ [89]. Chui et al. [90] showed a drive-current improvement of up to $ 50\,\%$ at a gate length of $ 50\,\mathrm{nm}$ for n-channel MOSFETs with $ Si_{0.987}C_{0.013}$ incorporated in the source and drain regions. Shallow Trench Isolation

Mechanical stress induced from Shallow Trench Isolation (STI) can not be neglected in the sub-micron regime at small active areas [91]. STI is able to generate large stress parallel to the channel (lateral) and in the direction along the width of the transistor (transversal). Reducing the transistor width boosts the compressive stress in the channel by the shallow trench effect and has been found to enlarge the hole mobility [92]. Strain Technologies in High Volume Production

The local strain approach proved to be more appropiate for industrial exploit. Therefore, the first strain technologies in high volume production evolved on the basis of uniaxial process-induced strain. Intel [87], IBM [88], Freescale [93], and Texas Instruments [86], integrate selective epitaxially growth techniques at their $ 90\,\mathrm{nm}$ technology node.

Stress levels in the range from $ 500-900\,\mathrm{MPa}$ are achieved, depending on the Ge content of the $ SiGe$ compound and the distance to the channel[94], enabling a saturation drain current increase up to $ 20\%-25\%$ for p-channel MOSFETs [87,93] and up to $ 10\%$ for tensile uniaxially stressed n-channel MOSFETs[87]. AMD and IBM developed in a joined effort a less complex technique [79]. Together with epitaxial films in the source and drain regions tensile and compressive capping layers on top of the transistors are used as local stressors [95,80].

$ Si_{3}N_{4}$ is able to exhibit compressive or tensile strain depending on the deposition conditions. First, a highly tensile Si nitride layer is deposited via thermal Chemical Vapor Deposition (CVD) over the whole wafer. Afterwards the layer is etched away selectively for the p-MOS active areas. Then, a compressive $ Si_{3}N_{4}$ layer is deposited via plasma assisted CVD. Afterwards the compressive nitride layer is etched away at the n-channel MOSFET active areas, yielding n-channel transistors under tensile and p-channel transistors under compressive uniaxial strain. Drive current enhancements of $ 11\%/20\%$ for n/p-channel MOSFETs have been shown for this dual stress liner technique [79].

Figure 2.7: Combining selective epitaxial growth in source and drain regions and a stress liner to introduce tensile uniaxial stress for n-channel MOSFETs and compressive uniaxial stress for p-channel MOSFETs.
Today, strain techniques are mandatory to sustain the pace in scaling. Joining two or more strain techniques in one device (Fig. 2.7) is a logical consequence when increasing strain levels even further. For instance, n-channel MOSFEETs uniaxial tensile strained via cap films and p-channel MOSFETs with selective epitaxially grown films, providing compressive stress, have been demonstrated by [96]. Horstmann et al. [84] showed a nice example of how to combine different strain techniques on SOI CMOS. They demonstrated an optimized stress integration scheme, combining an embedded $ SiGe$process and a compressively stressed liner film for p-channel MOSFETs, while a stress memorization process and a tensile stressed liner film are used for n-channel MOSFETs. After optimization, p/n-channel saturation drive current enhancements of $ 53\%/32\%$ were obtained, demonstrating the process compatibility and strain additivness of the manufacturing approach.
next up previous contents
Next: 2.3 Ferroelectric Gate Stacks Up: 2.2 Strained Interfaces Previous: 2.2.1 Global Strain

T. Windbacher: Engineering Gate Stacks for Field-Effect Transistors