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2.3.2 Applications

Due to the dedication of this work to gate stacks for field-effect transistors, I will concentrate on the applications of ferroelectric gate stacks for non-volatile RAM applications. There are several design concepts taking advantage of these materials. The initially developed FRAM exhibits a similar design concept as Dynamic Random Access Memory (DRAM), and therefore is exploited as an analogy to a capacitor and not as a gate stack material. The Ferroelectric Field-Effect Transistor (FeFET) utilizes the polarization of the ferroelectric material within the gate stack. Ferroelectric Thin-Films in FRAM

Non-volatile FRAM is based on the polarization reversal by an externally applied electric field of metal-ferroelectric-metal capacitors[111,112]. The logic states of $ 1$ and 0 are mapped to the positive and negative remanent polarization state, respectively. The destructive readout procedure is realized by the displacement current. FRAM is appealing due to its write and read cycle times in the sub- $ 100\,\mathrm{ns}$ regime and low power consumption, in comparison to other non-volatile memory technologies. Ferroelectric memory integrated in silicon CMOS was shown in $ 1987$. The chip contained only $ 256$ bits, and each bit contained two PZT capacitors forming a non-volatile shadow RAM. Although the cell size was large and the density low, it initiated further higher density test chips and ferroelectric random access memory products[113,114]. Despite the quite successful demonstration of ferroelectric memories utilizing PZT, difficulties to reach read/write cycles above $ 10^{12}$ started the investigation of other ferroelectric thin-film materials[115]. Relevant alternative materials are $ Sr Bi_{2} Ta_{2} O_{9}$ (SBT)[116], $ \left(Bi La\right)_{4}Ti_{3}O_{12}$[117], $ Ba Mg F_{4}$, $ Bi_{4} Ti_{3}O_{12}$[118], and $ Pb_{5}Ge_{3}O_{11}$[119]. The target of these investigations was to find a ferroelectric material exhibiting little or no degradation of the switchable ferroelectric polarization caused by typicall read and write operations. Among the alternative ferroelectric materials, $ Bi$-based compounds showed the biggest improvement in read-write cycle endurance, but only SBT has reached the market in FRAM products[120].

Another approach in order to increase the read-write endurance is to utilize Non-Destructive Readout (NDRO) for the ferroelectric capacitor polarization state[118]. Since many memory applications demand more read than write operations, a NDRO will reduce the wear of the ferroelectric capacitor. Unfortunately, all proposed NDRO ferroelectric memories seem to exhibit a common data disturb problem raised by partial back switching of the remanent polarization state during the each read cycle, resulting in a long term degradation of the read signal margin (loss of data state retention)[121].

Since the advent of FRAM, efforts on PZT capacitor process development and Destructive Readout (DRO) design for reliability yielded FRAM products with almost unlimited read-write endurance ($ >10^{15}$) and $ 10$ years of data retention for industrial temperature range specifications of $ -40$ to $ 85^{\circ}C$[122,123]. Several commercial FRAM devices feature a Two Transistors Two Capacitors (2T2C) cell with $ 0.5\,\mu\mathrm{m}$ minimum Complementary Metal Oxide Semiconductor (CMOS) gate length [124]. The ferroelectric capacitors of these devices are built on top of a field oxide in a way that the accompanying transistors are neighboring and each component of the cell exhibits a uniquely defined area. This so called Capacitor Over Field Oxide (COFO) architecture requires a relatively large cell size ($ 60\,F^{2}$, $ F$ denotes the metal half-pitch) for the employed 2T2C devices. In order to increase the memory density also significantly smaller cell sizes ($ 33\,F^{2}$) incorporating One Transistor One Capacitor (1T1C) designs have been developed[125]. Applications for these FRAM devices span from electrical power meters, printer configuration memories, and data loggers to video games and toy watches. Due to the success of FRAM mass production at $ 0.5\,\mu\mathrm{m}$ and $ 0.35\,\mu\mathrm{m}$ and the appealing application for various stand-alone and embedded applications, several companies have strengthend their efforts on continued scaling for FRAM to benefit from higher capacity and higher density [126,127,128,129,130]. Further scaling efforts led to a change in the FRAM cell design, reducing the cell size to $ 18\,F^{2}$. This is realized by building the ferroelectric capacitor on top of a plug that connects it to the underlying access transistor. The Capacitor On Plug (COP) architecture has been demonstrated for $ 4$ and $ 64\,\mathrm{Mbyte}$ memories[131,132]. Ferroelectric Field-Effect Transistors (FeFETs)

Despite the successful application of FRAM in commercial products, the need for ever increasing packing densities, due to scaling, demands more space efficient designs. A FeFET represents a $ 1T$ cell and consists of a Metal Oxide Semiconductor Fiel-Effect Transistor (MOSFET) whose gate dielectric has been replaced by a ferroelectric. Additionally to the smaller cell size, the read operation is non-destructive. Unfortunately, these devices exhibit only short retention times as non-volatile memory [133,134,135]. The concept of the FeFET was presented by Ross in the form of a patent[136]. Despite the huge research efforts on FeFETs including diverse material combinations and layouts, FeFETs were not able to reach maturity for a commercial product. Nevertheless, the brilliant concept of the FeFET is still quite appealing and its advantages and disadvantages will be discussed in the sequel.

At first, one has to note that the CMOS integration issues for a FeFET are are a bit different to the FRAM case. A FRAM capacitor is about $ 100\,\mathrm{nm}$ or more afar from the MOSFET, so both devices are physically independent. For an ideal FeFET, the ferroelectric is in direct contact with the drain to source channel of the transistor (see Fig. 2.8(a)). Therefore, the ferroelectric is an active part of the transistor and the performance is hugely affected by its interface properties. This is also one of the most serious problems for FeFETs. The localized states and impurities at the interface strongly influence the transistor properties like threshold voltage, saturation voltage, and the C-V curve of the gate stack. Another potential problem of FeFETis the inter-diffusion between the ferroelectric and the $ Si$. This is analog to the interface problems for native $ SiO_{2}$ and high-k dielectrics in high performance MOSFETs (q.v. Section 2.1). The basic challenges for FeFETs are found in the enhancement of the retention time and the supression of parasitic effects like the charge traps at the $ Si$-ferroelectric interface.

Figure 2.8: Schematic views for the different FeFET designs.
\includegraphics[width=0.4\textwidth]{figures/} \includegraphics[width=0.4\textwidth]{figures/} \includegraphics[width=0.4\textwidth]{figures/}

A possible solution in order to circumvent the problematic interface is to employ an insulating buffer layer between the $ Si$ and the ferroelectric as shown in Fig. 2.8(b) resulting in a Metal Ferroelectric Insulator Semiconductor (MFIS) structure [135,134]. Various buffer layers such as $ SiO_{2}$, $ Ce O_{x}$, and $ Si_{3}N_{4}$ have been studied. $ H\!fO_{2}$ and $ H\!f\!AlO$ show auspicious results. For a gate stack built from $ Pt/SBT/Hf\!O_{2}/Si$ layers a retention time of $ 30$ days has been shown [135,137].

Additionally to a low density of interface states the band offset between silicon and the ferroelectric or the buffer must be large enough to impede electron injection during programming. For instance, despite the quasi perfect growth of the high-k $ Sr Ti O_{3}$ on $ Si$ by Molecular Beam Epitaxy (MBE), the small band offset of $ Sr Ti O_{3}$ on $ Si$ causes strong current injection and a compensation of the ferroelectric boundary charge by electrons[138,139,140]. Also more complex gate stacks have been studied such as the Metal Ferroelectric Metal Insulator Semiconductor (MFMIS) gate structure (as depicted in Fig. 2.8(c)) [133,135]. The benefit of these gate stacks lies in the already available optimized metal-ferroelectric-metal process from FRAMs. Furthermore, it is possible to match the charge between the ferroelectric and the buffer layer by adjusting the area ratio. A smaller area of the MFM structure in comparison to the IS structure below results in a lower field strength in the buffer. The maximum charge density of $ SiO_{2}$ is $ 3.5\,\mu\mathrm{C}/\mathrm{cm}^{2}$ and relates to an electric field of $ 10\,\mathrm{MV}/\mathrm{cm}$, which is pretty close to the breakdown field of of $ SiO_{2}$. Typical complex oxide ferroelectrics posses more than ten times higher polarization densities. Therefore, often subloops are utilized to avoid electrical breakdown of the buffer[135].

Ferroelectricity is not restriced to complex oxides and can be found in several material classes. For instance, Polyvinylidene Fluoride (PVDF) copolymers posses ferroelectric properties[141]. The incorporation of ferroelectric polymers as gate oxides is an interesting approach. It has the advantage of negligible inter-diffusion due to its processing at room temperature and the probably superfluous buffer layer. Successfull research has been carried out on $ Si$ substrates [142,143,144] as well as on entire field-effect transistors [145,146,147]. This opens up the prospect of cheap and flexible non-volatile memory. One has to note that the experienced switching times are significantly lower than those for oxide FRAMs, and thus the field of application will be different.

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Next: 2.4 Electrolytic Interfaces Up: 2.3 Ferroelectric Gate Stacks Previous: 2.3.1 Ferroelectric Materials

T. Windbacher: Engineering Gate Stacks for Field-Effect Transistors