2.5 Achievable Lower Bounds in Static and Dynamic Logic

To determine feasible lower values of the supply voltage, a set of tuned CMOS processes was numerically analyzed by means of process and device simulation. The resulting device data were used for performance analysis on the circuit level [61,62]. Both process and device simulation were done using the VISTA Technology CAD framework to allow for quick process design and evaluation [54,55,32]. For the electrical characterization of the devices MINIMOS [27,69] was used to calculate a matrix of drain currents $\ensuremath{I_{\mathit{D}}}\xspace (\ensuremath{V_{\mathit{G}}}\xspace ,\ensuremath{V_{\mathit{D}}}\xspace )$ over a range of and for the p-channel and n-channel transistors. Based on these data, a fast and accurate table-driven DC analysis of simple gates and inverters is possible ^2.2 [62]. The dynamic behavior was estimated from capacitance data obtained by AC analysis with MINIMOS.

Figure 2.5: Doping profiles of ULP n-channel and p-channel transistors designed for digital operation at $\ensuremath{V_{\mathit{DD}}}\xspace = \rm 200mV$ (process A)

Table 2.3: Simulated device characteristics. The threshold voltage was defined as $\vert\ensuremath{I_{\mathit{D}}}\xspace (\ensuremath{V_{\mathit{T}}}\xspace )\vert = \rm 1\mu A / \mu m$. All voltages are in V, all currents are in A/$\rm\mu m$

process
A	0.2	0.067	-0.059	$0.14\cdot 10^{-6}$	$0.27\cdot 10^{-6}$	$16.7\cdot 10^{-6}$	$B.4\cdot 10^{-6}$
B	0.5	0.260	-0.240	$0.7\cdot 10^{-9}$	$2.8\cdot 10^{-9}$	$25.6\cdot 10^{-6}$	$16.7\cdot 10^{-6}$

Table 2.4: Noise margins (in % ) for a simple inverter and a 3-input NAND gate, and inverter delay, leakage time, switching energy, and static power consumption

process	${\ensuremath{{\mathit{NM}}_{\mathit{H}}}\xspace }_{\mathit{,inv}}$	${\ensuremath{{\mathit{NM}}_{\mathit{L}}}\xspace }_{\mathit{,inv}}$	${\ensuremath{{\mathit{NM}}_{\mathit{H}}}\xspace }_{\mathit{,gate}}$	${\ensuremath{{\mathit{NM}}_{\mathit{L}}}\xspace }_{\mathit{,gate}}$
A	28	23	13	39	0.29ns	7.2ns	0.65fJ	41nW
B	38	44	31	49	0.55ns	1.3$\mu$s	4.3fJ	0.88nW

The simulated processes were a $\rm0.35\mu m$ process (A) for static logic and a $\rm0.5\mu m$ process (B) for dynamic logic. The processes were designed for proper DC characteristics but were not optimized for speed. The essential simulation results are compiled in Tables 2.3 and 2.4. The device characteristics for process A are shown in Figs. 2.6 and 2.7. Figures 2.8 and 2.9 show the inverter transfer curves of both process A and B. The noise margins and the inverter delay for both processes are shown in Figs. 2.10 and 2.11 as functions of the supply voltage, and in Figs. 2.12 and 2.13 as functions of the operating temperature. It can be seen that a ring oscillator built with process A would work even at $\ensuremath{V_{\mathit{DD}}}\xspace =\rm 80mV$, and by using additional inverters at the gate inputs and outputs one could also design digital circuits for $\ensuremath{V_{\mathit{DD}}}\xspace < \rm 100mV$, but the overhead of the additional components would be considerable.

Figure 2.6: Input characteristics for process A ( $\ensuremath{V_{\mathit{DD}}}\xspace = \rm 200mV$)

Figure 2.7: Output characteristics for process A ( $\ensuremath{V_{\mathit{DD}}}\xspace = \rm 200mV$)

Figure 2.8: Inverter transfer characteristics for $\ensuremath{W_{\mathit{n}}}\xspace /\ensuremath{W_{\mathit{p}}}\xspace = 0.1...10$, process A ( $\ensuremath{V_{\mathit{DD}}}\xspace = \rm 200mV$)

Figure 2.9: Inverter transfer characteristics for $\ensuremath{W_{\mathit{n}}}\xspace /\ensuremath{W_{\mathit{p}}}\xspace = 0.1...10$, process B ( $\ensuremath{V_{\mathit{DD}}}\xspace = \rm 500mV$)

To see how close the two processes are to the absolute lower limits for $\ensuremath{V_{\mathit{DD}}}\xspace$ we define the factors $X = \ensuremath{V_{\mathit{DD}}}\xspace /\ensuremath{U_{\mathit{T}}}\xspace$ and $\ensuremath{X_{\mathit{crit}}}\xspace = \ensuremath{V_{\mathit{DD,crit}}}\xspace /\ensuremath{U_{\mathit{T}}}\xspace$. Using (2.11) we get $\ensuremath{I_{\mathit{on}}}\xspace /\ensuremath{I_{\mathit{off}}}\xspace = \ma... ...ensuremath{V_{\mathit{DD,eff}}}\xspace }/{\ensuremath{U_{\mathit{T}}}\xspace })$, and we define

$$\ensuremath{X_{\mathit{eff}}}\xspace = \frac{\ensuremath{V_{... ...hit{off,n}}}\xspace \ensuremath{I_{\mathit{off,p}}}\xspace }}.$$ (2.23)

These data are compiled for the two processes listed in Table 2.5: The ratio $X/\ensuremath{X_{\mathit{crit}}}\xspace$ tell how close a technology is to the lower limit of $\ensuremath{V_{\mathit{DD}}}\xspace$, regardless of the circuit performance. $X/\ensuremath{X_{\mathit{eff}}}\xspace$ gives the percentage of $\ensuremath{V_{\mathit{DD}}}\xspace$ which is used up to fulfill the criterion (cf. Table 2.2); the remainder serves to increase the performance. $\ensuremath{X_{\mathit{eff}}}\xspace /\ensuremath{X_{\mathit{crit}}}\xspace$ is an indirect measure for the sensitivity of a process (for process A the ratio is 1.31; a value below 1 would mean a violation of the criterion).

Table 2.5: Supply voltage utilization

process			X
A	200mV	A3mV	7.8	4.2	3.2
B	500mV	238mV	1B.6	B.6	B.2

From these data one can conclude that the limits for the supply voltage will be around 200mV for static logic and 500mV for dynamic logic with a fan-in of 3 at $\rm T=300K$.

Figure 2.10: Noise margins and delay time vs. $\ensuremath{V_{\mathit{DD}}}\xspace$, process A

Figure 2.11: Noise margins and delay time vs. $\ensuremath{V_{\mathit{DD}}}\xspace$, process B

Figure 2.12: Temperature sensitivity of process A ( $\ensuremath{V_{\mathit{DD}}}\xspace = \rm 200mV$)

Figure 2.13: Temperature sensitivity of process B ( $\ensuremath{V_{\mathit{DD}}}\xspace = \rm 500mV$)

Footnotes

... possible^2.2

This method was a precursor of the device model developed in Section 4.3.