2.1 Subthreshold Leakage

Since the early days of the MOS transistor, its switching capability has been exploited by a wide variety of applications. By applying a high or low voltage on the gate contact, the current flow between source and drain can be switched on or off, respectively. The off-state current was supposed to be very small, in fact, early analytical models for the electrical behavior of MOS transistors like the low-level SPICE models were even assuming a zero off-state current [37]. Commonly used equations for deriving the drain current were based on the well-known quadratic transfer curve of a MOS transistor. Below a certain gate-source voltage, called ``threshold voltage'', the drain current was supposed to be zero.

Surely, this has been a good approximation for quite some time when long channels and high supply voltages were used. Then the semiconductor industry started shrinking the devices to increase their density on a chip leading to a higher power dissipation since the active chip area stayed the same or was even increased to benefit from a higher system complexity. Additionally, the electric fields in the device were constantly increasing because the voltage drops over the gate oxide and the channel stayed the same while their sizes were reduced, leading to reliability concerns.

Consequently, the supply voltage was decreased to overcome these problems though the scaling method applied to the supply voltage has been much more conservative than the one for the device geometry [7,62]. The threshold voltage was decreased, accordingly, to maintain good driving capabilities.

As a result, the off-state current gradually became a limiting factor for down-scaling the threshold voltage since it determines the power consumption of a chip in its idle state. It could not be ignored longer and new physical models had to be applied to correctly describe the device behavior in the so-called subthreshold or weak-inversion regime [13,17,28].

Basically, three different regimes can be defined for the operation of a MOS transistor. Based on the inversion condition of the channel, these regimes are called weak inversion, moderate inversion, and strong inversion. In general, two mechanisms are responsible for the current flow: drift and diffusion.

Under weak inversion the channel surface potential is almost constant across the channel and the current flow is determined by diffusion of minority carriers due to a lateral concentration gradient. Under strong inversion there exists a thin layer of minority carriers at the channel surface and a lateral electric field which causes a drift current. The moderate inversion regime is considered a transition region between weak and strong inversion where both current flow mechanisms coincidently exist [65].

In the weak-inversion (or subthreshold) regime, the drain current depends exponentially on the gate-source voltage [65]

$$I_{\mathrm{d,weak}} \propto \exp \left( \frac{ {V_{\mathrm{gs}}}}{n\cdot V_\mathrm{T}} \right) ,$$ (2.1)

where $V_\mathrm{T}$ is the temperature voltage derived from

$$V_\mathrm{T} = \frac{k\cdot T}{q}$$ (2.2)

with $k$ being the Boltzmann constant, $T$ the absolute temperature, and $q$ the electron charge.

The subthreshold slolpe factor $n$ of a long-channel uniformly doped device can be calculated using simple expressions for the gate and bulk capacitances $C_\mathrm{g}$ and $C_\mathrm{b}$, respectively

$$n = 1 + \frac{C_\mathrm{b}}{C_\mathrm{g}} .$$ (2.3)

with

$$C_\mathrm{b} = \frac{{\epsilon}_{\mathrm{si}}}{w_\mathrm{d}}$$ (2.4)

and

$$C_\mathrm{g} = \frac{{\epsilon}_{\mathrm{ox}}}{t_{\mathrm{ox}}} .$$ (2.5)

In the latter equations ${\epsilon}_{\mathrm{ox}}$ and ${\epsilon}_{\mathrm{si}}$ denote the dielectric constants of the oxide and silicon, respectively, $w_\mathrm{d}$ is the depletion width under the channel, and $t_{\mathrm{ox}}$ is the gate oxide thickness.

The exponential subthreshold behavior can be explained by the exponential dependence of the minority carrier density on the surface potential which, itself, is proportional to the gate voltage. On a semi-logarithmic scale the transfer (or $I_{\mathrm{d}}$- $V_{\mathrm{g}}$) curve in the subthreshold regime will, therefore, be a straight line.

The slope of this line is called ``subthreshold slope''. The inverse of this slope is usually referred to as ``subthreshold swing'' $S$, given in units (mV/decade) and can be derived from (2.1)

$$S = n \cdot V_\mathrm{T} \cdot \ln(10).$$ (2.6)

In this equation the factor $\ln(10)$ results from the logarithmic scale with base 10 used to extract the subthreshold swing.

Due to the bulk effect the subthreshold swing of a conventional MOS transistor in bulk technology will always be higher than a certain optimum value which is roughly 60 mV/dec at room temperature, and which can be calculated by setting $n$ equal to 1 in (2.6) which means that the bulk effect is fully suppressed

$$S_{\mathrm{opt}} = V_\mathrm{T}\cdot \ln(10) .$$ (2.7)

In a realistic case $n$ will always be larger than 1. Therefore, the actual subthreshold swing $S$ will always be larger than $S_{\mathrm{opt}}$ depending on how well the channel surface potential can be controlled by the gate contact.

A small subthreshold swing is highly desired since it improves the ratio between the on- and off-currents. This requires that the bulk charge in the depletion region under the channel changes as little as possible when the gate voltage varies, therefore $C_\mathrm{b}$ should be small. Any additional bulk charge increases the voltage drop between the channel surface and the bulk contact, thus reducing the impact of the gate voltage on the surface potential.

A small $C_\mathrm{b}$ can be established by a light bulk doping $N_\mathrm{bulk}$ under the channel since the depletion width in (2.4) is proportional to the inverse square root of the doping level:

$$w_\mathrm{d} = \sqrt{\frac{2\cdot {\epsilon}_{\mathrm{si}} \cdot \phi}{q\cdot N_\mathrm{bulk}}}$$ (2.8)

with $\phi$ being twice the bulk Fermi potential.

Fig. 2.1 shows a couple of transfer curves of a quarter-micron MOS transistor for different bulk doping levels. There exists a doping for which the subthreshold swing has an optimum. For higher doping levels the bulk effect becomes stronger like described above.

Figure 2.1: Transfer curves of a 0.25 $\mu$m MOS transistor for different bulk doping levels. The doping is varied from 10$^{16}$ cm$^{-3}$ to 10$^{19}$ cm$^{-3}$ with an exponent step size of 0.25. The drain voltage is 1.5 V.

For very low doping levels this behavior is reversed, caused by an effect similar to the punchthrough effect [74] explained in Section 2.2. To demonstrate this, two devices with different bulk doping levels are investigated in the weak inversion regime under a constant drain current condition of 46 pA. Device $\alpha$ has a bulk doping of 3.16$\cdot$10$^{16}$ cm$^{-3}$, Device $\beta$ has a bulk doping of 10$^{17}$ cm$^{-3}$. Their operating points are indicated in Fig. 2.1.

Fig. 2.2 shows the two-dimensional potential distribution of the two devices. It can be seen that for Device $\alpha$ the drain and source depletion regions reach closer together due to the decreased doping level, and almost merge beneath the channel region.

Figure 2.2: Potential distribution in units (V) of Device $\alpha$ (top) and Device $\beta$ (bottom).

Therefore, the actual current path between drain and source penetrates deeper into the bulk, as depicted in Fig. 2.3 which shows the two-dimensional current density for Device $\alpha$. Fig. 2.4 compares the electron concentrations of the two devices across a vertical cut-line in the channel middle. Device $\beta$ has the maximum electron concentration at the surface whereas for Device $\alpha$ the maximum is clearly under the surface. As already mentioned above, both devices deliver the same drain current.

Figure 2.3: Current density in units (A/cm$^{-2}$) of Device $\alpha$.

Figure 2.4: Vertical electron concentration in the channel middle for Device $\alpha$ and Device $\beta$.

As a result of the increased distance of the current path to the surface, the gate contact loses more and more control over the channel which can be accounted for by a virtual increase of the gate oxide thickness and, therefore, a smaller gate capacitance according to (2.5).

For MOS transistors built in Silicon-On-Insulator (SOI) technology the subthreshold swing is usually better than in bulk technology. In fact the subthreshold swing of SOI devices can even reach the optimum value given in (2.7) depending on whether their bulk is fully depleted or partially depleted [14]. This makes SOI a promising candidate for ultra low-power CMOS applications though a lot of improvements to current process technologies still have to be made until this new technique can be applied to commercial products on a large scale [15].