At this point it only should be recalled that our approach uses Minkowski operations initially used in image processing [13]. The application of these operations to pattern transfer and modeling of etching and deposition is explained in [14].
In this paper we also show inclusion of layout information since the integration of the overall process simulation flow, from the layout to the final electrical and capacitive characterization is an important point in three-dimensional topography simulation for semiconductor applications.
Many non topography related tools with FEM methods and most of the device simulators using finite volume discretization are mesh based and therefore need a conversion from the topography representation to a grid format. At this point of interfacing between tools there is always a restriction of the accuracy to the resolution of the grid used as base for representing the surface. Since the accuracy of cellular approaches is always restricted to the minimal size of the cell, a careful balance between accuracy and CPU time has to be found.
In contrast to cell based approaches level set methods have a more accurate representation of surfaces and interfaces within their internal data representation. Even though they run into triangulation problems, if they have to be coupled with non level set tools. The triangulation can be done very easily for curved surfaces and arbitrarily oriented planes, where cellular approaches have weaknesses, especially when the planes are only slightly tilted against the axes of the grid. Nevertheless level set techniques require a time dependent adaptive meshing resulting in a large number of small triangles, if sharp corners have to be resolved, which are implicitly given in our cellular material representation. But this is a general and inherent problem of representing three-dimensional surfaces by a discrete number of two-dimensional polygons.
Based on our cellular approach we already successfully implemented such linked simulations and show reasonable fast and accurate simulations for DRAM cells and interconnect structures in [15]. The topography simulator makes use of either the layout information itself or of aerial images from lithography simulation to apply patterned masks on arbitrary structures. After the topography of the structure is generated by simulating the manufacturing process step by step, the geometry is converted to a mesh format suitable for the subsequent capacitance and resistance calculations with the FEM programs SCAP and STAP [16]. In this paper we restrict ourselves to show only an explanatory example of mask generation within our topography simulation, since this procedure is already presented in detail in [15].
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