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Next: 9 Conclusion Up: VLSI Performance Metric Based Previous: 7 Noise Margins, Inverter

8 Application

 To obtain the raw device data, MINIMOS [8] is used as device simulator and the device structures can be generated either by coupled process simulation, or, with an additional program, from analytical profile descriptions.

Table 4 shows results from a pocket-implanted LDD NMOS device with Lnom= 0.18$\mu$m, tox= 5nm, and Xj= 0.09$\mu$m designed for operation at VDD= 1.5V. The system parameters used for analysis were ld= 7 and a= 0.1 (interconnect capacitances were not considered). The evaluation was carried out for the nominal case (`nominal') and two worst-case corners (`a': T=Tmax=125$^{\circ }$C, channel and pocket implant doses, and L reduced by 20%; and `b': T=Tmin=0$^{\circ }$C, channel and pocket implant doses increased by 50%, and L increased by 20%). The data `c' are the same as `a' except that tox was reduced instead of the channel and pocket implants (to obtain the same shift in VT,lin). Each of these evaluations takes a CPU time of about 5 minutes on an HP735 workstation. The errors of the inverter gain and noise margins were determined from device-level simulations of an inverter with MINIMOS-NT and are typically in the order of 5%.


  
Table 4: Performance of a pocket-implanted LDD NMOST (L=0.18$\mu$m, VDD= 1.5V)
case VT,lin td 1 Es fc,max $\frac{f_{c,max}}{f_{c,min}}$ NM Ainv
  [V] [ps] [fJ] [GHz]   [Vdd]  
nominal 0.44 47.6 18.1 3.0 8.5e4 0.36 9.7
a: $\textcolor{red} {N_{ch}\downarrow T\uparrow L\downarrow}$ 0.21 34.2 27.2 4.2 7.3e0 0.29 6.1
b: $\textcolor{blue} {N_{ch}\uparrow T\downarrow L\uparrow}$ 0.67 92.6 19.3 1.5 2.6e9 0.44 34.2
c: $\textcolor{orange}{t_{ox}\downarrow T\uparrow L\downarrow}$ 0.23 35.9 19.8 4.0 7.1e1 0.32 9.9
error           -2.7% 3.6%
1 k1=0.67, k2=2.5 k3=1 (CMOS with slow PMOST)

The curves in Figs. 7-10 are the inverter delay, switching energy, maximum clock frequency, and clock frequency margin fc,max/fc,min for the three cases. From Fig. 10 and Table 4 it can be seen that the device fails at corner `a' because fc,max/fc,min is too small for dynamic logic. The noise margins, however, are still 30%VDD, which would allow static-logic operation.


  
Figure 7: Inverter delay td vs. VDD
\begin{figure} \epsfxsize=8cm \epsfbox{lp-td.eps}\end{figure}


  
Figure 8: Switching energy Es vs. VDD
\begin{figure} \epsfxsize=8cm \epsfbox{lp-Es.eps}\end{figure}


  
Figure 9: Maximum clock frequency fc,max vs. VDD
\begin{figure} \epsfxsize=8cm \epsfbox{lp-fc.eps}\end{figure}


  
Figure 10: Clock frequency margin fc,max/fc,min vs. VDD
\begin{figure} \epsfxsize=8cm \epsfbox{lp-fm.eps}\end{figure}

The impact of supply and threshold voltage on maximum clock frequencyand switching energyis shown in Figs. 11 and 12. For the simulations tox was varied from 1nm to 18nm, and fc,max and Es were plotted over VDD and the extracted VT,lin. To find an optimum device, one can, e.g., pick a contour in Fig. 11 according to the required performance and then, along this contour, find the minimum Es in Fig. 12.


  
Figure 11: Maximum clock frequency fc,max vs. VDD and VT,lin
\begin{figure} \epsfxsize=9.5cm \epsfbox{lpx-fc.eps}\end{figure}


  
Figure 12: Switching energy Es vs. VDD and VT,lin
\begin{figure} \epsfxsize=9.5cm \epsfbox{lpx-Es.eps}\end{figure}

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Next: 9 Conclusion Up: VLSI Performance Metric Based Previous: 7 Noise Margins, Inverter

G. Schrom, V. De, and S. Selberherr: VLSI Performance Metric Based on Minimum TCAD Simulations