1.3 Motivation for Novel Processing Techniques

In any research and technology field, there is a constant drive for innovation. Microelectronics, and more precisely, processing tools for microelectronics, are no exception. Since the initial introduction of the basic processing steps to generate transistors, there has been a constant innovation for new materials, structures, devices, and even processing steps. The first transistor has very few similarities to the common transistor in use today. Figure 1.1 depicts how the semiconductor technology has scaled since the early 1970's and some projections into the near future. It can be observed that Moore's law is still expected to endure for the next several years [154].

Figure 1.1: Comparison of sizes of semiconductor manufacturing process nodes since the early 1970s.

The reduction in size, which for the most part follows Moore's law, became only possible because of innovations in processing and material technologies. In order to continue this miniaturization trend, novel processing techniques have been introduced. Some of those processes and their modeling techniques are discussed in this work.

The constant reduction in device sizes demands a reduction in thermal oxidation times, since high temperature processes influence the distribution of impurities in the silicon bulk at the Si-SiO$ _2$ interface. Therefore, a novel process is required which can grow high quality oxide at low temperatures. Although oxide deposition processes exist, which can deposit SiO$ _2$ at low-enough temperatures, the grown oxide is of low quality. Recently, NAOS has been suggested in order to solve this issue as it can grow high quality oxides at much lower temperatures than thermal oxidation. NAOS is discussed in some detail in Section 3.3.

In addition to a reduction in the technology node, there is a constant drive in the semiconductor industry to fit as much memory capacity as possible within the area of the chip. There is a desire to provide memory capacities which have the capability to store the complete amount of human activities. The drive to achieve this lofty goal has lead researchers onto a path where memory was no longer laid out in two-dimensional patterns along the area of the chip, but rather three-dimensional structures were introduced. One such emerging technology is the three-dimensional BiCS memory recently introduced by Toshiba Corporation, but not yet in full production. It is suggested that the BiCS flash memory has the potential of up to 10Tbit/chip. This novel memory technology will be discussed in further detail in Section 4.2.

The AFM is a tool which has been used for many decades in order to read bumps and protuberances on a nanosized section of a desired surface. However, it has been found that it can also be used to generate patterns on a silicon surface using oxide growth. This processing technique is now capable of generating patterns with sizes much smaller than those covered by traditional lithography techniques. As scaling continues, as is suggested in Figure 1.1, such processes garner more interest. As the capability and knowledge regarding the utilization of the AFM for surface patterning grew, new devices were introduced and the full potential for this processing technique were investigated. A method to use an AFM to generate nanodots for high density storage was introduced, as well as a suggestion that an AFM can be used to generate nanowires, essential to the fabrication of the SiNWT. Technologies using an AFM and LON are covered in Section 2.4.

So far, it appears that the miniaturization of the technology node is the major cause for the introduction of novel processing techniques. However, the true driving force behind most innovations in the semiconductor industry has to do with economic potential of a technology versus its financial burden. Some process technologies do not necessarily introduce any technical solutions to existing problems, but are much more cost-effective and easy to use when compared to their alternatives. Spray pyrolysis deposition is an example of such a technology. Spray pyrolysis is used to deposit material on the surface of a semiconductor wafer. The simplicity of the process means that a laboratory or a start-up need not invest much in order to have its own deposition tool. In addition it has been shown that materials deposited using spray pyrolysis can be further annealed to grow, e.g., vertical nanowires with excellent gas-sensing properties. More information regarding the spray pyrolysis deposition process can be found in Section 4.1.

L. Filipovic: Topography Simulation of Novel Processing Techniques