5.2.1 Conventional EEPROM Devices

The basic operating principle of an EEPROM has been presented by KAHNG and SZE in 1967 at Bell Laboratories [275]. The device consists of a control gate and a floating gate on top of a conventional MOS transistor, see Fig. 5.25. A thin tunnel dielectric separates the floating gate from the channel. It must be thick enough to allow up to 10$ ^5$ writing and erasing cycles without breakdown -- common thicknesses are 6-8nm. Applying a high positive voltage (about 8-12V) on the control gate raises the potential of the floating gate by capacitive coupling. The high electric field in the tunnel dielectric ($ \approx$ 10$ ^9$V/m) leads to FOWLER-NORDHEIM tunneling of electrons from the substrate to the floating gate. The charge on the floating gate changes the threshold voltage of the underlying MOS transistor and is retained even if the control gate voltage is removed. A retention time of 10 years is required for consumer applications like memory cards. While EEPROM cells offer random access for writing and erasing of individual bits, Flash cells can be programmed selectively but erased only at once. This has the advantage of lower cell size. Due to the high electric field in the dielectric, degradation or even breakdown of the dielectric is a major concern. A comprehensive survey of NVM technology is given in [276] and [277].

Figure 5.25: The standard EEPROM device.


A. Gehring: Simulation of Tunneling in Semiconductor Devices