5.2.1.1 Static SILC in EEPROMs

The speed of the programming and erasing process is one of the main figures of merit of an EEPROM cell. Therefore, strong electric fields are applied at the control gate to allow FOWLER-NORDHEIM tunneling of carriers during programming and erasing cycles. However, due to this repeated high-field stress, trap centers in the dielectric are formed which allow trap-assisted tunneling at low fields and thus reduce the retention time of the devices. This additional current at low bias is known as stress-induced leakage current (SILC) and represents one of the major reliability concerns in contemporary EEPROM devices [196,219]. In the left part of Fig. 5.26 measured SILC after different stress times for a MOS capacitor with a dielectric thickness of 5.5nm is shown [189]. The trap-assisted tunneling model outlined in Section 3.8.2 yields excellent agreement with the measured data if the trap concentration is used as a fitting parameter dependent on the stressing time (the model parameters are stated in the figure caption). The transition from the region of mainly trap-assisted tunneling for $\ensuremath{V_\mathrm{GS}}<5$V to the region of FOWLER-NORDHEIM tunneling for $\ensuremath{V_\mathrm{GS}}>5$V is clearly visible. The right part of Fig. 5.26 shows the trap occupancy $f_\mathrm{T}$ across the gate dielectric of a MOS capacitor using the gate voltage as parameter. The regions near the gate (right) and near the substrate (left) are only sparsely occupied. Near the gate, the emission time is much smaller than the capture time, and near the substrate, the trap energy lies above the electron energy in the cathode. Some of the trapped electrons face a triangular barrier for the emission process, giving rise to an additional peak in the trap occupancy near the gate side (the anode) of the dielectric. This is due to the wave function interference in the FOWLER-NORDHEIM region (the oscillations are also observed in the emission time of the traps shown in Fig. 3.19).

Figure 5.26: Comparison of simulations with measurements of an MOS capacitor with a dielectric thickness of 5.5 nm (left) [189]. The trap energy is 2.7 eV, the phonon energy 130 meV and the HUANG-RHYS factor 10. The trap concentration was set to 9e17 cm-3, 1e17 cm-3, 3e16 cm-3, and 3e15 cm-3 to fit the measurements (from top to bottom). The trap occupancy across the gate dielectric at different gate voltages (right).

A. Gehring: Simulation of Tunneling in Semiconductor Devices