5.2.2.1 Non-Volatile Memory Devices Based on Trap-Rich Dielectrics

A SONOS (silicon-oxide-nitride-oxide-silicon) device is a non-volatile memory where the charge is stored in a layer of trap-rich dielectric material instead of a floating gate as in an EEPROM. Fig. 5.31 shows an example where a layer of Si$_3$N$_4$ is sandwiched between two layers of SiO$_2$. Electrons tunneling from the substrate are trapped and redistribute themselves in separate trapping centers. This has the advantage that the charge is stored independently in the traps. A leaky path in the tunnel dielectric cannot lead to full charge loss, as it is the case in conventional EEPROM devices. Therefore, reliability and retention time is increased [282,283,209,284,285,168,286,287,288,289,290,291].

Figure 5.31: SONOS device structure. A layer of trap-rich dielectric, such as highly defective Si$_3$N$_4$, is sandwiched between two SiO$_2$ layers.

The band diagram along the dielectric of such a device is shown in Fig. 5.32 for the programming, storing, and erasing processes. By applying a positive voltage at the gate contact, electrons tunnel through the tunnel dielectric into the trap region. The traps are filled with electrons and become negatively charged. Because of the tunnel dielectric this charge is stored even if the bias is removed. To erase the memory cell, a negative voltage is applied on the gate contact, leading to a reduced potential barrier and a high tunneling current of electrons out of the traps. Important device parameters are the charging and discharging current through the dielectric, the drain current in the on- and off-state, and the retention time.

Figure 5.32: Conduction band edge in a SONOS device for the programming, storing, and erasing process.

Figure 5.33: Transient trap occupancy in the trap-rich dielectric layer of a SONOS device which is discharged from $t=$0 s to $t=10^9$ s.

The trap-assisted tunneling model can be applied to simulate device characteristics of this device, where three layers of SiO$_2$ have been used and the trap concentration and trap energy level in the middle layer was chosen to resemble a layer of silicon nitride. The transient trap occupancy for a discharging process starting from an initial condition of 2V at the gate contact is shown in Fig. 5.33. Initially the traps are filled. Over time, the electrons leak through the lower dielectric into the channel. After $10^9$s almost no more charge is stored in the trap-rich dielectric.

A. Gehring: Simulation of Tunneling in Semiconductor Devices