5.2.2.2 Multi-Barrier Tunneling Devices

One of the main shortcomings of conventional EEPROM devices is that the current in the on-state and off-state -- the programming and leakage currents -- flow through the same tunnel dielectric and face the same energy barrier. They cannot be optimized independently: Increasing the thickness of the tunnel dielectric reduces the leakage, but also reduces the on-state current and thus increases the programming time. Multi-barrier tunneling devices offer a solution to this problem. Planar localized-electron device memory (PLEDM) cells have been presented by NAKAZATO et al. in [292], and promising results have been reported [293,294,295,296]. The principle of a PLEDM is to put a PLED transistor (PLEDTR) on top of the gate of a conventional MOSFET, as shown in Fig. 5.34. The charge on the memory node, which acts as a floating gate, is provided by tunneling of carriers through the PLED transistor which consists of a stack of Si$_3$N$_4$ barriers sandwiched between layers of intrinsic silicon. Upper and lower barriers prevent diffusion from the polysilicon contacts, while the middle barrier -- the central shutter barrier (CSB) -- blocks the tunneling current in the off-state. The PLED transistor has two side gates which are separated by a thin dielectric layer. In the on-state the energy barriers are heavily reduced by the voltage on the side gates, causing a strong tunneling current to flow at the interface to the side gate dielectric. In the off-state, however, the side gates are turned off and the energy barrier blocks the leakage current. As in a conventional EEPROM, the charge on the memory node is used to control the underlying MOS transistor. Only a small amount of charge has to be added to or removed from the memory node to change the state of the memory cell.

Figure 5.34: Conduction band edge energy in the PLEDM device.

Figure 5.35: PLEDM calibration of the tunneling current density for a single Si$_3$N$_4$ layer with 1.5 nm and 2 nm thickness.

For the simulation of such devices measurement results for a single Si$_3$N$_4$ barrier diode [296] have been used to calibrate the model, as shown in Fig. 5.35. For calibration the carrier mass in the dielectric was used as a fit parameter. Electron and hole masses of 0.5m$_0$ and 0.8m$_0$ where found to reproduce the data. The Si$_3$N$_4$ barrier was modeled with a barrier height of 5eV and a conduction band offset of 2eV to the silicon conduction band edge with the relative dielectric permittivity being 7.5. Fig. 5.36 shows in the left part the conduction band edge along the PLEDTR and in the right part the electron wave function for the case of a top contact bias of 1V and a side gate bias of 2V. The wave function has been acquired using the QTB method described in Section 3.5.4.

Figure 5.36: PLEDM conduction band edge (left) and electron wave function (right) for a top contact bias of 1 V and a side gate bias of 2 V.

The effect of the position and size of the central shutter barrier as well as the effect of shrinking the stack width have been investigated. Two cell states have been assumed: an on-state with 3V applied on the top contact and the side gate, and an off-state with 0.8V applied on the memory node and 0V on the side gate. In both states the charging and discharging current was extracted. The PLEDTR had a stack width of 180nm and a stack height of 100nm. The thickness of the upper and lower barriers was set to 2nm. The left part of Fig. 5.37 shows the effect of different CSB thicknesses on the on- and off-current of the device. While the on-current is hardly influenced by the different thicknesses, the off-current is very sensitive to it. Also, the position of the CSB is critical, because for a CSB located near the memory node, the energy barrier will be reduced in the off-state by the charge on the memory node. If, on the other hand, the CSB is placed near the top contact, the energy barrier is not suppressed in the off-state and the off-current is much lower. The on-current is also reduced by this effect, but the amount of reduction is much lower as compared to the off-current, due to the fact that the on-current mainly depends on the voltage of the side gate. Thus, the $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratio increases with the thickness of the central shutter barrier and is highest for a CSB located near the top contact. Such an asymmetry in the IV characteristics depending on the position of the central shutter barrier has already been observed experimentally [296].

In [297] the feasibility of very narrow silicon-insulator stacks is shown. This encourages the assumption that a reduction of the stack width is possible. Fig. 5.37 shows the on- and off-currents of the device with a CSB thickness of 10nm for a stack width of 140nm down to 20nm. It can be seen that a reduction of the stack width leads to increasing on-currents and decreasing off-currents. The reason is that the current in the on-state, which mainly flows as a surface current near the side gate, is not reduced by the decreased width of the stack. It even increases for very low stack widths which may be due to the fact that the energy barriers at the side of the stack merge for very low stack widths. The off-current, on the other hand, is directly proportional to the stack area and can thus be directly downscaled by shrinking the stack width. For a stack width of 20nm, $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratios of more than 10$^{32}$ can be reached.

Figure 5.37: On-current density and off-current density as a function of the thickness of the central shutter barrier (left) and the stack width (right).

A. Gehring: Simulation of Tunneling in Semiconductor Devices