2.1 Historical Overview

The field-effect transistor (FET) was first proposed by LILIENFELD in 1926 and patented in 1930 [1]. However, the practical implementation was impossible due to material-related problems. On December 23 $^\mathrm{rd}$ 1947, BARDEEN and BRATTAIN, scientists at AT&T Bell Labs who worked in the group of SHOCKLEY, discovered the transistor effect [2,3,4], for which they received the NOBEL prize in 1956. The first integrated circuit was demonstrated by KILBY at Texas Instruments in 1959. In the same year NOYCE and MOORE, who had been working with SHOCKLEY, founded the company Fairchild Semiconductor, where they introduced the first commercially used semiconductor transistors^2.2. The first field-effect transistor based on MOS technology was developed by KAHNG and ATALLA in 1960 [5]. MOORE, NOYCE, and GROVE left Fairchild Semiconductor and founded the company Intel in 1968. Soon, this company became the leading manufacturer of microprocessors. In 1965, MOORE reckoned that the number of transistors per integrated circuit approximately doubles every year, and he contributed this to three main effects: improvements in lithography, increased chip size, and gain from circuit and design innovation [6]. In 1975 he updated his statement and predicted that the number of transistors doubles every eighteen months to two years [7]. This statement has become widely known as MOORE's law, and it became the main paradigm of the microelectronics industry in the following decades.
The steady reduction of MOSFET device dimensions and integration densities found a theoretical basis in 1974 when DENNARD presented the constant-field scaling law [8] according to which the device dimensions can be reduced without altering the electrical characteristics if all dimensions, voltages, and doping concentrations are scaled in such a way that the electric field in the device remains constant. Hence, lengths and voltages are reduced by a factor $s$, while doping concentrations are increased by the same factor. This is shown schematically in Fig. 2.2 for a scaling factor $s=2$ [9]. BACCARANI et al. presented a generalized scaling law [10] which takes into account that voltages cannot be reduced by the same factor as lengths. Instead, if voltages are scaled with a factor $s_2$ and lengths with a factor $s_1$, doping concentrations must be scaled by $s_1^2/s_2$.

Figure 2.2: Constant-field scaling of MOS devices.

In 1992, the Semiconductor Industry Association (SIA) published the National Technology Roadmap for Semiconductors (NTRS) which was later replaced by the International Technology Roadmap for Semiconductors (ITRS). This document represents a collaborative effort to identify critical topics in semiconductor development. Every two years, comprehensive forecasts of the main technological parameters of semiconductor technology are published.
Two of the most important parameters to quantify device scaling are the DRAM (dynamical random-access memory) half pitch and the MPU (microprocessor unit) half pitch, defined as half the spacing of two connecting metal lines. Another important parameter is the gate length of MOSFETs , where a distinction between printed and physical gate length must be made. Table 2.1 shows the predictions of the 2001 edition of the ITRS [11] compared with the values of the 1999 and 1997 edition.

Table 2.1: Predictions of the ITRS 2001 compared with the predictions of 1997 and 1999. Values are in nm. In the ITRS 1999 and 1997 no predictions for the physical gate length, and in 1997, no MPU half pitch is given.

	DRAM			MPU		MPU			MPU
	$1/2$ pitch			$1/2$ pitch		Printed			Physical
	2001	1999	1997	2001	1999	2001	1999	1997	2001
2001	$130$	$150$	150	150	180	90	100	120	65
2002	115	130		130	160	75	85		53
2003	100	120	130	107	145	65	80	100	45
2004	90	110		90	130	53	70		37
2005	80	100		80	115	45	65		32
2006	70		100	70		40		70	28
2007	65			65		35			25
2008		70			80		45
2009			70					50
2010	45			45		25			18
2011		50			55		30
2012			50					35
2013	32			32		18			13
2014		35			40		20
2016	22			22		13			9

It can be seen that the predictions of each roadmap exceed the ones of the predecessor, an observation which has been called roadmap acceleration: While in 1997 the 70nm DRAM half-pitch was predicted for the year 2009, it was predicted for 2008 in 1999, and the 2001 roadmap sees it in the year 2006.

Figure 2.3: MOSFETs with 60 nm (left) and 10 nm (right) gate length [12,13]. The gate dielectric thicknesses are 1.5 nm and 0.8 nm, respectively.

This continuous scaling has led to the development of transistors with gate lengths as small as 60nm or even 10nm in experimental devices, as shown in Fig. 2.3 [12,13]. However, major obstacles arise when devices are scaled to such small dimensions. A. Gehring: Simulation of Tunneling in Semiconductor Devices