2.2 Obstacles to Device Miniaturization

Several topics can be identified which represent severe handicaps to a further scaling of CMOS devices. Fig. 2.4 shows a cut through a typical CMOS inverter which consists of an nMOS and a pMOS device separated by shallow trench isolation (STI) [14,13]. Crucial topics which must be taken into account to allow further device shrinkage are highlighted [15]. They will be briefly discussed in the following sections.

Figure 2.4: Important topics for further miniaturization of CMOS devices [15].

Subsections

• 2.2.1 Channel
• 2.2.2 Gate Stack
• 2.2.3 Source and Drain
• 2.2.4 Gate Dielectric

A. Gehring: Simulation of Tunneling in Semiconductor Devices