2.1.1 Advanced Gate Design in Submicrometer CMOS Technologies

To achieve the surface-channel operation of both, -channel and -channel devices for the common anti-punch-through implants and well doping, the gate work function should be adapted. Several approaches to meet this goal have been proposed in the literature:

1. -type gate is used for -channel and -type gate for -channel devices. After an eventual threshold-adjustment implant both MOSFETs remain surface-channel devices. We speak about the ``dual gate CMOS technology'' [512][346][276][202][93][60]. The gates are usually doped by implantation, simultaneously during source and drain formation.
2. Polycrystalline SiGe gate is used for both devices. By increasing (mole fraction of Ge) the valence band of the SiGe material is shifted upwards. For doped alloy, it has been demonstrated that the gate work function is reduced by for compared to (degenerate value) [250][249]. Note that no significant changes in the work function have been observed for doped gates. By choosing the proper content of Ge in the gate, a trade-off between the -channel and -channel MOSFET optimization can be made, designing both devices with a surface channel.
3. -type gate is used for -channel and gate for -channel devices [367]. The manufactured gates, discussed in [367], have a work function which increases from an approximately mid-gap value at low implantation doses to the value of a degenerate gate at high implantation doses. By choosing a low implantation dose the proper threshold voltage and the surface-channel operation are achieved for -channel MOSFETs. However, I expect that the work function of lightly doped gates is strongly influenced by the trapping of free carriers. The grain size and their distribution, trap density at the grain boundaries, trap distribution in the energy space and various fairly unknown peculiarities of the polysilicon/oxide interface (fixed charge, traps and dipoles) determine the Fermi level position and the band-bending in lightly doped polysilicon gate. The previous quantities are not only just partially known, but are also strongly process dependent.
4. For both devices a refractory metal which has a mid-gap work function, is deposited directly on the gate oxide. A CMOS technology with Mo gates is demonstrated in [262]. The work function of polycrystalline Mo is with respect to vacuum, namely with respect to the intrinsic level in silicon . Proper threshold voltages for both -channel and -channel devices are obtained by the well implants. W-gate CMOS technology is presented in [513][254][227]. The work function of polycrystalline W is or with respect to in silicon. Both devices can be designed with surface channels. In addition, both Mo and W are low-resistive interconnectors. A drawback is that the use of refractory-metal gates is not compatible with standard CMOS technology. Note that refractory-metal silicides have different work functions than the metals themselves. For example: MoSi has a work function of or with respect to in Si. To achieve a low threshold voltage of -channel MOSFETs with MoSi gate a compensate channel implant is necessary, which produces the buried channel [468][312].
5. Compound gates like WSi-TiN are used for both devices [248]. A TiN layer is deposited on the gate oxide and determines the work function difference. The work function for this type of gate is measured in the range to , namely to with respect to the intrinsic level in silicon. As a result, -channel MOSFETs can be designed as surface-channel devices. WSi-TiN is a good interconnector, as well.

The first approach, with the and gates for -channel and -channel devices, respectively, is the simplest between the previously discussed and compatible with standard technology. A refractory metal-silicide layer over the polysilicon gates significantly lowers the interconnection resistance [361]. Therefore, the dopant concentration in the polysilicon gates may be reduced compared to the conventional gates doped by diffusion. This allows the gates to be doped by implantation. In the dual gate technologies this can be simultaneously performed with the implantation of the source and drain junctions.

The main parameter which determines the electrical characteristics of the gate is the activated net impurity concentration near the gate/oxide interface. This concentration ought to be sufficiently high, which is one of the key issue in processing the implanted gates.