2.2 Analytical Modeling of MOS Structures with Nondegenerate Gate



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2.2 Analytical Modeling of MOS Structures with Nondegenerate Gate

 

A voltage drop always occurs in the gate when the gate-bulk bias is applied, because the electric field is nonvanishing through the whole polysilicon-gate/oxide/silicon structure. Conventional degenerately doped gates are highly conductive and the voltage drop in the gate may be assumed as negligible. In the case of nondegenerate doping, the voltage drop in the gate cannot be neglected, especially in thin-oxide devices. An analytical modeling of MOS devices, assuming the gate as a non-equipotential area, has been proposed in [293]. However, the detailed calculations have not been carried out and the voltage drop in the gate is judged as a secondary effect. The high-frequency (HF) - curves of the polysilicon/oxide/silicon and of the polysilicon/oxide/polysilicon structures have been discussed theoretically and experimentally in [520]. In this section an analytical model of the polysilicon/oxide/silicon structure is presented [165]. To estimate the effect of the nondegenerate gate on device characteristics we adopted a simple model for the polysilicon gate in the first approximation; the polycrystalline Si is treated as single-crystal Si. The influence of traps at grain boundaries in polysilicon and traps at the gate/oxide interface is discussed later. Some shortcomings of the physical model will be clarified while comparing the calculations with experimental data in Section 2.3.





Martin Stiftinger
Sat Oct 15 22:05:10 MET 1994