3.4  Simulation Results


Figure 3.6.: Modulation of wS   and wT   during the logic operation for different input patterns.


Figure 3.7.: ΔVG   as a function of RG   for different values of VS,C   .

In order to analyze the TiO2   -based memristive circuit (Fig. 3.2), the nonlinear model is used for each TiO2   memristive switch and thus, coupled with the equation Eq. 3.4, Eq. 3.13–Eq. 3.22 are numerically solved for both S  and T  . Fig. 3.6 shows the modulation of the tunnel barrier widths    w
     S   and               w
                T   during the implication operation for all possible input patterns (State 1–State 4) described in Table 3.2. It illustrates that for pulse durations between 1–10 ms, only in State 1, the target memristor (T) is switched and in all other cases both S  and T  are left unchanged. Accordingly, correct logic behavior is achieved for all input states and the logic result is stored as the final resistance state of T  . Here, the initial tunnel barriers are wo ff =  1.86 nm  and won  =  1.43 nm  which are equivalent to Mo  ff =  1M  Ω  and M     =  20k Ω
   on  at the readout voltage of 0.2 V (Fig. 3.4). The circuit parameters R    =  4.41 k Ω
  G  , VSET   =  - 2.28  V  , and VCOND    =  - 2.14  V  are optimized to minimize the SDE as is explained below.


Figure 3.8.: Total state drift as a function of VS,C   .

According to Fig. 3.6, the dominant SDs occur in State 1 (Fig. 3.6a) in T  (SD     =  w   - w
   T1      T      on   ) and in State 3 (Fig. 3.6c) in T  (SDT2   =  wo ff - wT   ). Therefore, maximizing the modulation of the voltage                     VG   between State 3 and State 1 (ΔV     = |V    -  V   |
    G       G3     G1 ) minimizes the possible SDEs in T  . Fig. 3.7 shows ΔVG   as a function of RG   for different values of VS,C   where

VS,C =                    .

As follows from Fig. 3.7, the optimum RG   corresponds to the maximum ΔVG   which maximizes the modulation of the voltage drop on T  between State 3 and State 1 and thus minimizes the SDEs in                     T  shown in Fig. 3.6. Therefore, it is uniquely defined by the memristor’s properties, VSET   and            VCOND   . By using Fig. 3.7, an optimum R
  G   is obtained for each value of V
 S,C   and then one can optimize              V
              S,C   to minimize the gate error (Fig. 3.8).

In fact, the voltage modulation ΔVG   increases with increased VCOND   and minimizes the SD in memristor T  . However, an increase in VCOND   results in an increasing error on memristor S, because it tends to switch S  in State 1 (SDS1  =  wo ff -  wS   ) and State 2 (SDS2  =  wo ff -  wS   ). Therefore, there is an optimum VS,C   for which the total state drift (SDtotal   ) defined as normalized root mean square error as shown in Fig. 3.8. Optimum VCOND   and RG   are determined at any    VSET   by

            ∘ ----------------------------------
              SD2T1  +  SD2T3 +  SD2S1 +  SD2S2
SDtotal  =  ------------------------------------.
                      2(wo ff -  won )


Figure 3.9.: Cumulative state drift effect in T  for State 3.

TiO2   memristive switches enable stateful implication logic by serving simultaneously as non-volatile memory and logic gates. Although the digital data is stored in the high- and low-resistance state of the memristive device, the internal state variable w  shows analog behavior (Fig. 3.6). Therefore, during the logic operations the voltage drops on S  and T  tend to push w  toward won   , also when their switching is undesired. This causes the state drift error, which accumulates in sequential logic steps and results in a one-bit error after a certain number of implication operations. Thus, refreshing circuitry is required to avoid this error [162]. Fig. 3.9 shows the cumulative SD in T  during 20 implication operations with 1 ms pulse duration when T  and S  are in high and low resistance states, respectively (State 3). It illustrates that after 14 steps the sate variable w  is equal to the median value of (wo ff +  won )∕2 ≃ 1.65 nm which can be readout either as high- or low-resistance state. Whereas any resistance switching in State 3 is considered as an undesired switching, the initial logic state of              T  has to be rewritten before w  reaches 1.65 nm. It is worth mentioning that the linear model predicts a SD of 48.9% [162] for a particular design example which means a refreshing is required after each implication operation. Compared to the nonlinear ionic drift model, the linear drift model exhibits higher state drift values since it assumes that the state drift is directly proportional to the current or voltage of the memristive devices. However, according to experimental data, the ionic drift velocity shows an exponential dependence on the applied current or voltage [148] which is taken into account in the nonlinear model by Eq. 3.20 and Eq. 3.21. Once again one has to note that, as high switching voltages are used for (high-speed) computing, the memristor nonlinear model has to be used to take the tunneling effect and dynamical memristor behavior into account.


Figure 3.10.: Optimized VSET   pulse amplitude as a function of the pulse duration (IMP speed) based on the linear and the nonlinear memristor models.


Figure 3.11.: Average implication operation energy (--
EIMP   ) as a function of the IMP speed based on the linear and the nonlinear memristor models.

Fig. 3.10 shows only a slight increase of the optimized V
 SET   pulse amplitude with the implication switching time decreased in contrast to the linear model. This results in large power consumption benefits at higher IMP speed (Fig. 3.11) and shows a good agreement between simulations based on the nonlinear model and the available experimental data (see Fig. S5(b) in Supplementary Information of [75]) which demonstrates a decrease in switching energy of a TiO2   memristive device with the pulse duration decreased. In fact, Fig. 3.11 demonstrates that when the linear model is used, event the trend of the average implication energy consumption (--
  IMP   ) is wrongly predicted as it shows an increase with the IMP speed increased.

--         ∑ 4
E     =  1-     E    (i),
  IMP     4       IMP

where EIMP (i)  denotes the implication energy consumption when the memristive devices       S  and                T  are initially in State i  .