Novel Implication Logic Gates Using STT-MTJs

4.3 Novel Implication Logic Gates Using STT-MTJs

4.3.1 Device Principles

The basic structure of the magnetic tunnel junction consists of a free and a fixed (pinned) ferromagnetic layer separated by a tunneling oxide (Fig. 4.8). The magnetization of the free layer has a bistable configuration and can be switched between a parallel and an antiparallel state compared to the fixed magnetization direction of the pinned layer. The MTJ exploits the tunnel magnetoresistance effect associated with the relative angle between the magnetizations of the free and the pinned layers. An antiparallel alignment results in a high-resistance state (HRS; $RAP$ ) of the MTJ, while the parallel alignment places it in a low-resistance state (LRS; $RP$ ). The MTJ resistance modulation is described by the tunnel magnetoresistance (TMR) ratio and is defined as $TMR = (RAP - RP )∕RP$ . Nowadays, the tunneling oxide is usually MgO. Due to the enhanced spin filtering, MgO-based MTJs exhibit a high TMR ratio which is facilitated to read-out the MTJ resistance state via the TMR effect [38]. The TMR ratio record of up to 604% [182] reported in MgO-based MTJs is close to the theoretical maximum ( $~$ 1000%) [183, 184].

Figure 4.8.:

Sketch of basic MTJ structure with a bistable (parallel/antiparallel) magnetization configuration in the free layer.

The magnetic state of the MTJ free layer can be switched either by a magnetic field or by a spin-polarized current via the STT effect. Compared to the first generation of MTJs, which utilized a magnetic field for switching, the STT switching technique exhibits pure electrical read/write operations and renders the current-carrying wire generating the magnetic field superfluous. This brings significant advantages with respect to scalability and energy consumption [22]. It makes the STT-MTJ a suitable candidate for a universal memory which combines the advantages of CMOS compatibility, non-volatility, high switching speed, high integration density, unlimited endurance, and scalability. Furthermore, the STT-MTJ shows memristive behavior [61, 71] as its magnetic state and thus the corresponding resistance is a function of the historic profile of the current passing through the MTJ. Indeed, the STT-MTJ exhibits the memristor fingerprint [71] characterized by a pinched $i - v$ hysteresis loop [185, 186].

In the following, the STT-MTJ-based realization of the stateful implication logic operation is demonstrated by using the conventional implication gate topology and a novel topology which significantly improves the performance of the STT-MTJ-based implication logic gates (Fig. 4.12). In the STT-MTJ-based logic gates, due to the magnetic bistability of the MTJ caused by an intrinsic damping in its magnetic free layer [23], the magnetization of the free layer can relax to its initial state when there is enough time (in the range of sub-nanosecond [187]) between sequential logic operations. Therefore, unlike the TiO $2$ and the domain wall based logic gates, where the state drift errors are accumulated as described before, the need for refreshing circuitry in the STT-MTJ-based stateful logic systems is eliminated. In order to analyze and compare the performance of the STT-MTJ-based logic gates, considerations regarding the reliability of these gates are explained in the next section.

4.3.2 Reliability Modeling and Analysis

Initially, there was no performance analysis regarding STT-MTJ-based logic gates available, which are very favorable for stateful logic applications as discussed before. However, as it is shown in the following, the reliability analysis of the stateful logic operations is as an essential prerequisite for benchmarking and performance comparison of different STT-MTJ-based logic architectures. Here, based on the mechanism of the conditional switching behavior in stateful logic, a framework needed to perform the reliability modeling and analysis for the STT-MTJ-based stateful logic gates is described and used for investigating, optimizing, and comparing different STT-MTJ-based logic gates and architectures.

4.3.2.1. Reliable Switching

In order to analyze the stateful logic gates explained before and to further extend stateful logic to cover more devices and circuit topologies, the conditional switching behavior of a memristive device can be described by using Fig. 4.9, which shows the switching dynamic of a memristive element as a function of the applied voltage/current pulse amplitude. The horizontal axis denotes the voltage (or current) level applied to a memristive element for a specific time (a pulse duration of $τ$ ). The solid curve indicates the high-to-low (or low-to-high) resistance switching behavior of the device where the vertical axis represents a normalized internal state variable of the device. The internal state variable can represent the deterministic switching model of the memristive device (e.g. $w (t)$ in a TiO $2$ memristive switch or the relative domain wall position $r$ in a spintronic memristor) or the switching probability of a spintronic memristive element with a stochastic switching model (e.g. $Psw$ in a STT-MTJ). Region A shows a reliable switching region for which the dashed line represents the minimum reliable switching voltage ( $Va$ ) (or a corresponding current $Ia$ ). Region B denotes a reliable non-switching region for which the dashed line represents the maximum reliable non-switching voltage ( $Vb$ ) below that the disturbance due to the applied voltage/current is negligible and it cannot force a switching event. When $Vb ⁄= 0$ , the memristive device has a nonzero switching voltage/current threshold which is in general a function of the pulse duration $τ$ .

Figure 4.9.:

Normalized internal state variable of a memristive device as a function of the applied voltage.

In the TiO $2$ or the DW-TMR memristive implication logic gates explained before, there are four possible high-to-low resistance switching cases depending on the initial resistance states, when the voltage pulses $V SET$ and $V COND$ are applied to the gates. However, only when both $S$ and $T$ are in the high resistance state (State 1), the voltage drop on $T$ (the current flowing through $T$ ) is higher than $Va$ . In the other cases, the voltage drops on $S$ and $T$ are below $V b$ and, therefore, undesired switching events are avoided. For example, as in State 3 $S$ is in the low-resistance state, the voltage or current of $T$ is decreased and thus its high-to-low resistance switching is avoided. This conditional switching behavior, which comprises a set of desired and undesired switching events, corresponds to implication logic. Similarly, in a STT-MTJ-based logic gate, depending on the initial resistance states of all MTJs a target (output) MTJ is switched or not. Reliability of such a conditional switching behavior can be defined as a function of the switching probabilities ( $P sw$ ) of desired switching events as well as $1 - P sw$ for undesired switching events. This basic discussion can be used to study, optimize and compare STT-MTJ-based logic gates. Furthermore, it provides a better understanding of the conditional switching mechanism in stateful logic which paves the way for the proposal of logic gate with novel topologies. In the following, a SPICE model of the STT-MTJs is presented and modified to have the capability of calculating the reliabilities and error probabilities in the STT-MTJ-based logic gates.

4.3.2.2. Modified STT-MTJ SPICE Model

The STT-MTJ SPICE model presented in [188] includes a (deterministic) decision circuit to control a bistable circuit which shows an immediate switching between parallel and antiparallel states (Fig. 4.10). The decision circuit comprises two capacitors (C $1$ and C $2$ ) excited by two current sources ( $I1$ and $I2$ ) connected in parallel to realize the relationship between the critical switching time and the critical switching current.

In fact, the rate of the charge/discharge of the capacitors is a function of the current flowing through the MTJ ( $i$ ) and is determined by [188]

( [ i ]) I1 = exp - Δ 1 - ------------ IC0(AP →P )

(4.10)

and

( [ ] ) -----i------ I2 = exp - Δ 1 - . IC0 (P →AP )

(4.11)

$Δ$ is the thermal stability factor and is equal to $Eb∕kBT$ . $Eb$ represents the energy barrier between the parallel and the antiparallel magnetization states of the MTJ, $kB$ is the Boltzmann constant, and $T$ is the temperature. $IC0 (AP→P ) > 0$ and $IC0 (P →AP ) < 0$ denote the critical currents for the antiparallel-to-parallel and parallel-to-antiparallel switching cases and are extrapolated to the critical switching time $t0 = 1$ ns. It has been shown that the time required to charge the capacitors C $1$ and C $2$ by exactly 1 V with the capacitance of 1 nF are given by [188]

( [ ]) t = (1-nF--)(1-V-)-= 1 ns × exp Δ 1 - -----i------ C1 I1 IC0(AP →P )

(4.12)

and

( [ ] ) t = (1-nF--)(1-V-)-= 1 ns × exp Δ 1 - -----i------ . C2 I2 IC0 (P →AP )

(4.13)

In the thermally-activated switching regime (switching time $t >$ 10 ns), Eq. 4.12 (Eq. 4.13) is identical to the relationship between the critical switching time $tp$ and the critical switching current ( $IC$ ) of antiparallel-to-parallel (parallel-to-antiparallel) MTJ switching as [188]

[ ] tp- IC = IC0 1 - Δ ln( ) . t0

(4.14)

As the critical values of switching time and current are usually defined for the MTJ switching probability of 50% [188], the decision circuit enforces an immediate switching to the bistable circuit as soon as the switching probability is 50%. The curve fitting circuit is used to take the voltage-dependent effective TMR ratio into account, which is important to determine the resistance-voltage characteristic of the MTJ. This SPICE model covers the major electrical characteristics of the STT-MTJs. It is, however, not possible to calculate the switching probabilities of the STT-MTJs required for reliability analysis and comparison of the STT-MTJ-based logic gates only based on this SPICE model (Fig. 4.11). Therefore, in order to calculate the STT-MTJ switching probability ( $P sw$ ), the theoretical expression for the thermally-activated switching regime [189] is used

( [ ( ) ] ) τ IMTJ Psw = 1 - exp - --exp - Δ 1 - ------ , t0 IC0

(4.15)

where $IMTJ$ is current flowing through the MTJ and $τ$ is the pulse duration.

Figure 4.10.:

Simplified equivalent circuit of the MTJ SPICE model and the proposed error calculation circuit.

Figure 4.11.:

STT-MTJ switching probability as a function of the applied current based on the modified STT-MTJ SPICE model compared to the decision signal $V1$ from the (unmodified) SPICE model.

Eq. 4.15 has been experimentally verified in [49] and can be added to the STT-MTJ SPICE model for switching probability (error) calculations by using a curve fitting circuit shown in Fig. 4.10 characterized as

( ) P = 1 - exp - τ-I AP →P t0 1

(4.16)

and

( ) τ-- PP →AP = 1 - exp - t I2 . 0

(4.17)

Fig. 4.11 compares the experimental results from [49] with the unmodified and the modified STT-MTJ SPICE models. It illustrates that although the decision signals $V 1$ in the (old) STT-MTJ SPICE predicts the correct critical switching current where the probability of the switching is 50%, it cannot fit the experimental data equally well.

In order to calculate the current flowing through the STT-MTJs in the stateful MTJ logic gates (described later), the voltage-dependent effective TMR model [190] is used, which determines the resistance characteristic of the MTJs in the antiparallel MTJ state as a function of the MTJ voltage ( $v MTJ$ ) as

( ) R = R (1 + TMR ) = R (1 + -TMR0-----) . AP P v P v2MTJ- 1 + Vh2

(4.18)

$TMR0$ and $TMRv$ are the TMR ratio under zero and non-zero bias voltage across the MTJ, respectively. V $h$ is the bias voltage equivalent to $TMR = TMR ∕2 v 0$ .

4.3.3 Improved Implication Logic Gate

As explained before, due to the magnetic bistability of the MTJ, STT-MTJ logic gates eliminate error accumulation in stateful logic and thus are inherently suited for digital computing and are preferable over TiO $2$ -based or domain wall-based technologies, which exhibit error accumulation due to their analog behavior. In this section, STT-MTJs are employed to perform implication logic based on the conventional voltage-controlled (VC) implication gate topology (Fig. 4.12a) and a novel current-controlled (CC) topology (Fig. 4.12b). Based on the description of the reliable conditional switching cases (Section 4.3.2.1) and the modified STT-MTJ model (Section 4.3.3), the performance of these gates are compared and it is demonstrated that the proposed CC-IMP gate outperforms the conventional VC-IMP gate in terms of reliability and power consumption.

Figure 4.12.:

STT-MTJ-based implication logic gates based on (a) the conventional voltage-controlled and (b) the proposed current-controlled topologies.

Similar to the memristive stateful implication gate (Table 3.2), in the voltage- and current-controlled implication gates (Fig. 4.12a and Fig. 4.12b) the logic operation (N)IMP is realized based on a conditional switching in the target MTJ ( $T$ ). Depending on the initial resistance states of the source and the target MTJs, an AP–to–P STT switching event is enforced in the target MTJ only, when both MTJs are initially at antiparallel (high resistance) states (State 1). For the other input patterns (State 2, State 3, and State 4), the resistance states of the MTJs are left unchanged as shown in Table 3.2. In the MTJ-based voltage-controlled implication (VC-IMP) gate (Fig. 4.12a), the logic operation is executed by simultaneously applying the voltage pulses $VCOND$ and $VSET$ . As $|V | < |V | COND SET$ , the voltage drop on $S$ is smaller than the critical voltage level required for STT switching and thus $S$ is left unchanged. The resistance state of $S$ provides a voltage modulation across $T$ through $R G$ . Due to this modulation, $T$ switches, when $S$ is in the high resistance state (State 1), but remains unchanged, when $S$ is in the low resistance state (State 3).

In the CC-IMP gate (Fig. 4.12b) the logic operation is performed by applying the current pulse $I imp$ to the gate. $Iimp$ is applied in a direction which tends to enforce AP–to–P switching events to both MTJs. The current $I imp$ is split between $S$ and $T$ inversely proportional to the total resistance of each branch. The current split depends on the input pattern as the resistance value of each branch is a function of the logic state of its MTJ. According to Table 3.2 there are four possible AP–to–P switching events containing State 1 and State 3 for $T$ and State 1 and State 2 for $S$ .

Figure 4.13.:

AP–to–P switching probabilities of $T$ and $S$ in the CC-IMP gate as a function of $I imp$ .

In order to better understand the operation of the implication gate, Fig. 4.13 shows the switching probabilities of S ( $Ps$ ) and T ( $Pt$ ) as a function of the current level applied to the implication gate ( $Iimp$ ) for all possible AP–to–P switching events $P t1$ , $P t3$ , $P s1$ , and $P s2$ . The current direction of $I imp$ is fixed, so that only high-to-low resistance switching is feasible in both MTJs for any input combination. When both MTJs are initially in the high resistance state (State 1), low $I imp$ values ( $≈ 0.4$ mA) can not enforce any switching, because the currents flowing through both MTJs are below the required switching current.

For a correct implication logic behavior, $T$ ( $S$ ) must (not) switch to the low resistance state. Thus, $I imp$ has to be chosen in a way that $T$ exhibits a high switching probability and $S$ remains unchanged (within the reliable gap RG shown in Fig. 4.13). This gap is controlled by $R G$ as it limits the current flow through $S$ . In State 2 $S$ is in the high resistance state and the current flowing through $S$ is lower than the value required for STT switching due to $R G$ and the low resistance state of $T$ . In State 3, although $T$ is in the high resistance state, $Iimp$ does not switch $T$ ( $P ≃ 0 t3$ ) since $S$ is in the low resistance state. This requires a high enough $S$ resistance modulation (high TMR) and also restricts the upper limit for $RG$ . When both MTJs are in the low resistance state (State 4), there is no possible switching event as the direction of the $I imp$ is fixed.

The reliability of the implication operation in State 1 is proportional to the multiplication of the probability of the desired switching event in $T$ ( $Pt1$ ) and the term $1 - Ps1$ , where $Ps1$ is the probability of the undesired switching event in $S$ . Therefore, in State 1, the error probability ( $E1$ ) is

E1 = 1 - Pt1(1 - Ps1 ).

(4.19)

In State 2 and State 3, there are only undesired switching events ( $P s2$ and $P t3$ ) in $S$ and $T$ , respectively. Therefore, the error probabilities are given by

E2 = Ps2, E3 = Pt3.

(4.20)

When both MTJs are in the low resistance state (State 4), there is no possible switching event and the error probability $E 4$ is zero. It is obvious that a reliable logic behavior of an operation is ensured only, when the logic gate exhibits correct functionality for all input patterns. Therefore, by assuming equal incidence probabilities for all input patterns, the average implication error probability ( $--- E IMP$ ) is obtained by

--- ∑4 E = 1- E = 1-(1 - P + P P + P + P ). IMP 4 i 4 t1 s1 t1 s2 t3 i=1

(4.21)

From a circuit point of view, the parameters ( $Iimp$ and $RG$ in the CC-IMP and $VCOND$ , $VSET$ , and $RG$ in the VC-IMP gates) can be optimized to minimize the error probability $--- EIMP$ for given MTJ device characteristics. Fig. 4.14a shows the error probabilities $Ei$ for different input states of the CC-IMP gate as function of $Iimp$ for a fixed $RG$ with MTJ devices characterized by $TMR = 250%$ , $Δ = 40$ , $IC0 (AP → P ) = 325 μA$ , and $RP = 1.8 k Ω$ . $Iimp$ has to be high enough to enforce a desired switching of $T$ in State 1. However, there is an optimum $Iimp$ , as increasing $Iimp$ increases the probabilities for undesired switching events in both $T$ and $S$ in State 1, State 2, and State 3.

Figure 4.14.:

Error probabilities ( $Ei$ ) for different input states of the CC-IMP logic gate as function of (a) $Iimp$ and (b) $RG$ .

Figure 4.15.:

(a) Dominant error probabilities ( $E1$ and $E3$ ) for different TMR ratios. (b) Circuit parameters optimization in the CC-IMP gate with TMR ratio and optimum $RG$ and $Iimp$ of $250%$ , $0.8 kΩ$ , and $0.5 mA$ , respectively.

In the CC-IMP gate $R G$ provides a structural asymmetry which increases the current flowing through $T$ compared to $S$ , when both MTJs are in the high resistance state (State 1). Therefore, increasing $RG$ reduces the error probability $E 1$ as it increases (decreases) the probability of the desired (undesired) switching event $Pt1$ ( $Ps1$ ) as shown in Fig. 4.14b. However, its maximum value is limited by $E3$ . In State 3, $S$ is in the low resistance state and thus the current flowing through $S$ is increased as compared to State 1. Therefore, the current flowing through $T$ is decreased to a lower level, below the critical current required for the STT switching. Because a higher $R G$ decreases the effective resistance modulation of its corresponding branch (the source branch comprises $RG$ and $S$ ), it increases the error probability $E3$ (Fig. 4.14b).

As explained before, a higher $R G$ reduces the error probabilities in State 1 and State 2 but is limited by the required current modulation in State 3. The current modulation in State 3 relies on the modulation of the MTJ resistance between its antiparallel and parallel magnetization states described by the MTJ’s TMR ratio. From this follows that the TMR ratio is the main device parameter affecting the reliability of the implication gate. A higher TMR ratio provides a higher current modulation and allows higher values of $RG$ for CC-IMP circuit parameters optimization. Fig. 4.15a shows the two dominant error probabilities ( $E 1$ and $E 3$ ) for two different TMR ratios. It illustrates that a higher TMR ratio has a negligible effect on $E1$ but it decreases $E 3$ . Therefore, for MTJs with increased TMR, the CC-IMP gate with optimized circuit parameters exhibits a more reliable logic behavior. In fact, as the current modulation between State 1 and State 3 depends on the TMR ratio, a higher TMR ratio allows for higher values of $RG$ (lower $E1$ shown in Fig. 4.14b) when the circuit parameters are optimized. Fig. 4.15b shows an example of a two-dimensional circuit parameters optimization for the CC-IMP logic gate.

In order to compare the performance of the CC-IMP and VC-IMP gates, the circuit parameters are optimized and the error probabilities and the energy consumptions are calculated. According to Fig. 4.16, the optimal $RG$ of the implication gate based on the conventional topology (Fig. 4.12a) is higher by a factor of two to three as compared to the proposed topology (Fig. 4.12b). Furthermore, in the conventional voltage-controlled gate topology the current flowing through $RG$ is equal to the sum of the switching current $iT$ and the modulation current $iS$ ( $IG = iS + iT$ ) while it is only equal to the switching current $iT$ in the novel current-controlled gate topology ( $IG = iT$ ). Therefore, for a fixed current level and a given switching time, the implication energy consumption is about 60% lower in the novel implication gate topology than in the conventional topology. A comparison of the implication energy consumption in the two topologies is shown in Fig. 4.17a.

Figure 4.16.:

Optimized $RG$ in the conventional (VC-IMP) and the proposed (CC-IMP) implication logic gates depending on the TMR ratio.

Figure 4.17.:

(a) The IMP energy consumption and (b) the average error depending on the TMR ratio for both conventional and proposed topologies.

Robust implication logic behavior requires a high enough state dependent modulation in both topologies. This modulation on the target MTJ ( $T$ ) which is caused by the difference between the high and low resistances of the source MTJ ( $S$ ), is directly proportional to the TMR ratio of the MTJ. Therefore, from the device point of view, we expect that the error $--- EIMP$ decreases with the increase of the TMR ratio which is a determinant device parameter for the logic reliability. Fig. 4.17b demonstrates that the error $Eimp$ decreases exponentially with increasing TMR ratio. At a fixed TMR ratio the CC-IMP gate topology provides a higher modulation on $T$ , thus reduces the average error probability by about 60% as compared to the conventional one. As the proposed CC-IMP gate enables a more energy-efficient and reliable implementation for implication logic framework, in the following we employ the CC-IMP gate for the performance comparison between the STT-MTJ-based implication logic gates and the state-of-the-art (reprogrammable) gates.

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