4.2  Implication Logic Using DW-TMR Memristors

Combining the domain wall (DW) motion induced by the spin-transfer torque (STT) [44, 45] with the tunnel magnetoresistance (TMR) effect [169] has launched new concepts for spintronic memristive devices [61, 96, 64]. The TMR effect is observed as a change in the electrical resistance of a magnetic device depending on the relative magnetization states of two ferromagnetic layers separated by a non-magnetic insulating layer (whether ferromagnetic layers are in a parallel or an antiparallel alignment). Compared to the memristive devices based on ionic motion (e.g. TiO2   memristor), spintronic memristors are more favorable in terms of speed, endurance, fine-tunability, and CMOS compatibility [136, 65, 116, 81]. In this section it is shown that the implication logic operation can be implemented based on DW-TMR memristive devices (Fig. 4.2), with the DW positions serving as state variables. This enables stateful logic operations that extends spintronics from non-volatile memory to logic applications, for which the spintronic memristor serves simultaneously as gate and latch.

4.2.1  DW-TMR Memristor


Figure 4.2.: (a) DW-TMR memristor structure and its equivalent circuit. (b) A top view of the free layer of a DW-TMR memristor.

The STT effect allows to manipulate the local magnetization in a magnetic device by transfusion of magnetic momentum from a spin polarized current. Therefore, a spin-polarized current can induce motion in magnetic domain walls. Because of its potential applications, STT domain wall motion (STT-DWM) has generated wide interest and has been well studied theoretically and experimentally [170, 171, 172, 173, 174, 175, 176, 177]. In a spintronic device, when the total electrical resistance depends on the magnetization state, on one hand, and the current flowing through the device can modulate the magnetization state, on the other hand, the device exhibits memristive capabilities [60, 61, 62, 63, 64, 65, 66, 67]. In fact, the magnetization state and thus the electrical resistance of such a device becomes a function of the historic profile of the current or the voltage applied to the device which represents memristive behavior.

Fig. 4.2 shows the basic structure[96, 137] and a (possible) top view [64] of a domain wall tunnel magnetoresistance (DW-TMR) memristor comprising an insulating layer and two ferromagnetic layers, a reference layer with a fixed (pinned) magnetization state and a free layer which is divided into two segments by a magnetic domain wall. The electrical resistance of the device depends on the relative orientation of the magnetization directions. A complete antiparallel alignment results in a high-resistance state (HRS;                   RH   ) of the device, while a fully parallel alignment places it in a low-resistance state (LRS; R
  L   ). The total resistance (memristance) of the device is modeled by two resistors connected in parallel RP   and     RAP   as [137]

R   =  RL--
  P     r


R    =  -RH---,
  AP    1 -  r

where x  is the domain wall position, r  represent the relative DW position (0 ≤  r =  x∕L  ≤  1  ), and                      L  denotes the length of the free layer. Therefore, the i - v  characteristics of the device is obtained as

v =  R (r )i,


M  (r ) = R (r ) =  rR   +  (1 -  r)R  .
                       H              L

When the DW velocity VDW  (t)  is proportional to the applied current density (j(t) = i(t)∕A  ), the dynamics of r  is obtained as [137]

dr     1 dx     1             Γ DW
---=  -- --- =  --VDW  (t) =  ------jeff(t),
dt    L  dt     L              L



j   (t) =    0,      j (t) < jcr
  eff          j(t),  j (t) ≥ j

Γ DW   is a DW velocity coefficient related to the device characteristics and A  is the DW cross-sectional surface. The DWM appears when the current density j(t)  is above a critical current density (            jcr   ) [137]. Eq. 4.4 and Eq. 4.5 demonstrate that the device acts as a memristive system. Recently, a physical realization of DW-TMR memristive devices has been reported in [64].

4.2.2  Domain Wall Dynamics

The DW-TMR memristor model described above includes simplifying assumption from [137] regarding the dynamics of the current-induced DWM (VDW   ∝  jeff   ). Here, a more accurate modeling of the current-induced DWM is presented which can be used to drive the State equation (Eq. 2.15) of the DW-based devices operating as memristive systems (see Section 2.1.2).

The modified Landau-Lifshitz-Gilbert (LLG) equation [178] with an added spin-torque term [45] can be used to describe the magnetization dynamics of a current-induced DWM as [174, 175]

 ∂t = -γ0⃗m ×⃗
Heff + αm⃗ ×∂-⃗m-
 ∂t -jP-μB--
     s[                    (         ) ]
     ⃗                    ⃗
 (⃗u. ∇ )⃗m  - β ⃗m  ×   (⃗u. ∇ )⃗m. (4.7)

⃗m (r )  is a unit vector representing the direction of the local magnetic moments, γ0   is the gyromagnetic ratio,  ⃗
He ff   denotes the effective magnetic field, α  represents the Gilbert damping parameter. The third term in Eq. 4.7 represents the spin-torque term of the current flowing in the direction   ⃗u  , where                j  shows the injected current density, P  denotes the spin polarization of the current, μB   is the Bohr magneton, Ms   represents the saturation magnetization, and β  defines the strength of the non-adiabatic spin-torque.

By using the collective coordinate approach which assumes that the configuration of the DW can be explained by the collective coordinates the DW position (x  ) and the angle between spins at the wall center and the easy plane (ϕ  ), the LLG is simplified to Eq. 4.8 [179, 180].

d ˆt + αd-ˆx
 dt = β ĵ, (4.8a)
d ˆt - αd ϕ
 dˆt = sin(2ϕ) + ĵ, (4.8b)

where ˆt ≡  tv ∕λ
       c  , ˆx ≡  x ∕λ  , ˆj ≡  jP μ  ∕ (eγ  λK   )
          B     0    ⊥  , represent the aspect parameters time, DW position, and current density which are normalized to dimensionless units. Here, vc ≡  γ0λK  ⊥ ∕Ms   is a constant with the velocity dimension,      ∘  ------
λ =     J∕K  is the DW thickness, K
  ⊥ is the hard-axis anisotropy,     J  is exchange coupling constant, and K  denotes the easy-axis anisotropy.

4.2.3  DW-TMR-Based Implication Logic


Figure 4.3.: DW-TMR-based implication logic gate.

Fig. 4.3 shows an implication logic gate exploiting the DW-TMR memristive devices as non-volatile memory as well as logic gates. The implication operation is performed by applying the voltage pulses           VSET   and V
  COND  which tend to enforce high-to-low resistance switching in the memristive device      S  and T  .

The electrical resistances of S  and T  depend on the position of their DWs xS   and   xT   which act as the state variables. The realization of the implication logic operating relies on a threshold current density below that the DWs does not move. Similar to the TiO2   -based implication logic gate, a high-to-low resistance switching is enforced in the target device (T  ) only when both S  and T  are in the high resistance state (State 1 shown in Table 3.2). Therefore, the conditional switching behavior equivalent to the basic operation of the implication logic is feasible using DW-TMR memristors.

In order to analyze the DW-TMR-based implication logic gate (Fig. 4.3), Eq. 4.4–Eq. 4.6 are numerically solved for both S  and T  coupled with Eq. 3.4 where iS   and iT   are the currents following through                       S  and T  , respectively. MS   and MT   represent their memristances which are a function of        rS =  xS∕L  and rT  =  xT ∕L  , respectively.

4.2.4  Simulation Results and Discussion

When S  and T  are in the high-resistance state (State 1), the current passing through      T  (          jT1   ) is above the critical current jcr   required for the STT-DWM (Fig. 4.4). Due to the voltage drop on         RG   , the current passing through S  (jS1   ) is below jcr   and thus its DW does not move. Therefore, a high-to-low resistance switching is enforced only in T  and MS   is left unchanged (State 1 in Fig. 4.5). As during the switching MT   decreases, the current density jT1   (jS1   ) is increased (decreased). This acts as a positive feedback between jT1   and MT   which accelerates the current-induced DWM and allows reducing the time required for the implication operation. The memristor devices are characterized in [137] with physical dimensions and electrical parameters assumed as: the length of L =  200   nm, the width of z =  10   nm, the thickness of h =  7   nm, RH  =  7.5 k Ω  , RL  =  2.5 k Ω  , Γ v = 2 ×  1016  nm3  C - 1   , and                   - 2
jcr =  20 nA   nm   .


Figure 4.4.: Initial current densities passing through the DW-TMR memristor devices S  and T  as a function of               RG   .


Figure 4.5.: M
  S   and M
  T   during the implication operation for different initial logic states (State 1 – State 4) explained in Table 3.2.


Figure 4.6.: Implication operation energy (Ei   ) as a function of RG   in State i  .

The resistance states of S and T  are left unchanged for other combinations of initial states (State 2 – State 4 shown in Fig. 4.5). In fact, their current densities are below jcr   when they are initially in the high resistance state (j
 S2   in State 2 and j
 T3   in State 3 shown in Fig. 4.4). Therefore, the DW-TMR memristive gate exhibits the conditional switching behavior shown in Table 3.2. This is equivalent to the basic operation of the implication logic and enables spintronic stateful logic.

Fig. 4.6 shows the energy consumption of the DW-TMR gate (Ei   ) at different initial states (State                   i  ) as a function of R

      ∫  τimp
E  =        [M   i2+  M   i2 +  R   (i +  i )2]dt,
  i             S S      T T      G  S     T

According to Fig. 4.6, a higher RG   increases the implication energy consumption. However, its minimum value is limited by State 3 to provide a correct logic behavior as shown in Fig. 4.4. In fact, a higher                    RG   increases the difference between jT1   and jT3   and ensures that MT   is not switched in State 3. Therefore, Point A for which jS1 =  jT3   (shown in Fig. 4.4) indicates an optimum value of RG   to ensure the correct logic behavior in all states.

For more accurate analysis regarding the state drift errors, the one-dimensional model of magnetic DWs (see Section 4.2.2) has been used to investigate the DW dynamics in S  and T  during the implication operation. Here, coupled with Eq. 4.4 for S  and T  , Eq. 3.4 is numerically solved to calculate MS   (MT   ) as a function of xS   (xT   ), while the dynamics of xS   (xT   ) is obtained by using Eq. 4.8. The memristor device geometries are supposed as L  =  100 λ  , z =  4λ  , and the free layer thickness as h =  λ  . Fig. 4.7 shows the DW dynamics of S  and T for all possible inputs (State 1 to State 4). Due to their polarities, the voltage pulses VSET   and VCOND   tend to increase rS   and rT   to enforce parallel alignment between free and pinned layers of   S  and T  .


Figure 4.7.: The current signals (iS   and iT   ) and the DW position ratios (rS   and rT   ) of S  and     T  during the implication operation.

Since, the structure of the DW-TMR memristor devices is based upon existing magnetic memory technology it combines the advantages of CMOS compatibility, high speed, high density, almost unlimited endurance, and scalability and thus is very promising for spintronic memristors implementation [64]. However, although in stateful implication logic the DW-TMR memristors are used as two-resistance-state devices, they exhibits analog behavior as the DW displacement is continuous in value and is proportional to the amplitude of the injected current and the pulse duration. Therefore, similar to the TiO2   -based logic gates, this causes a state drift error during the implication operation. This error accumulates in sequential logic steps and is very unfavorable for stateful logic as it results in a computation error after a certain number of logic steps. According to Fig. 4.7, the major state drift error happens in x
  T   . It illustrates that after one implication operation the state drift error is about 10% and 5% in State 1 and State 3, respectively. Therefore, a refreshing is required after less than 10 logic steps as an accumulated error of >  50%  cause a one-bit error in the readout. In the next section the realization of implication logic using STT-MTJs is demonstrated, which does not suffer from error accumulation problems. It is based on the STT-MRAM technology which has recently been commercialized by Everspin [181].