3.3.2 Layout Set Example

One typical application for layout parameterization found in device engineering, is the analysis of sub-micron transistors with various channel and width sizes. The template transistor layout file is depicted in Figure 3.7. As the gate contacts and interconnect lines remain fixed, the problem cannot be solved just by scaling everything. In spite of being a simple example, it shows the advantages of using parameterized layout generation. In this example the rules-file shown in Figure 3.8 was used to obtain the results shown in Figure 3.9.

Due to the demonstration purposes of this example, several auxiliary variables were used in the rules-file increasing its size. Rather large step sizes are intentionally also used and consequently only few (six in this case) different output layouts are generated. In a real application this number can be much larger.

Table 3.1: Evaluate-functions list ($\alpha$ and $\beta$ are the step variables and $K_{*}$ are scale factors).

Function	Description
translate[LAYER $\alpha~\beta~Kx~Ky$]	Translates all polygon with layer name LAYER
	by vector $(\alpha \times Kx,~\beta\times Ky)$.
stretchUp[LAYER $\alpha~K$]	Stretches all polygons of layer name LAYER
	up by factor $\alpha \times K)$.
stretchDown[LAYER $\alpha~K$]	The same as above, but down.
stretchLeft[LAYER $\alpha~K$]	The same as above, but left.
stretchRight[LAYER $\alpha~K$]	The same as above, but right.
scale[LAYER $\alpha~K$]	Scales all polygons of layer name LAYER
	by factor $\alpha \times K)$.
scaleFixedPoint[LAYER $\alpha~\beta~Kx~Ky$]	Scales all polygon of layer name LAYER
	but the center remains fixed.
rotate[LAYER $\alpha~K$]	Rotates all polygons of layer name LAYER
	by angle $\alpha \times K)$.
rotateFixedPoint[LAYER $\alpha~K$]	The same as above, but in turn of the
	center of the polygon.
generateNoise[LAYER $\alpha~\beta$]	Makes the polygons of layername LAYER noisy.
	Noise amplitude= $\alpha$ and noise frequency= $\beta$.

Figure 3.7: NMOS transistor template layout.

Figure 3.8: Example of file with rules used in set generation.

Figure 3.9: Automatic generation of layout sets.