3.4 Layout and Lithography

Lithography is a major concern in integrated circuit fabrication. The continuous improvements in optical lithography are responsible, to a large extent, for the success of the semiconductor industry. Although its limits will be reached in less than 10 years [29] it is still the only viable technique for high wafer throughput available today.

Traditionally, as already stated in Section 1.1, the design and fabrication phases of VLSI integrated circuits are uncorrelated and circuit designers have only to obey the layout rules. These are, however, a compromise found for a given process when considering parameters as performance, reliability and yield. The layout design rules are usually conservative and sometimes not the best choice for a particular design. This is becoming worse in deep-submicron technologies as imaging systems are improving resolution-$R$ not only by decreasing the exposure wave length - ${\lambda}_w$, but continuously increasing the lenses Numerical Aperture^66#2 (NA), which in turn reduces the depth of focus (DOF) as given by the Rayleigh scaling equations:

$$R=k_1 \frac{{\lambda}_w}{\mathit{NA}},$$ (3.1)

$$\mathit{DOF}=k_2 \frac{{\lambda}_w}{\mathit{NA}^2}.$$ (3.2)

Yet, reducing the DOF causes severe restrictions to the maximum roughness allowed in the wafer surfaces [29], which is becoming a formidable problem, as planarization techniques are expensive and not extensively available. Some improvements in DOF and resolution are obtained using phase-shift masks that are supported by our layout editor.

Footnotes

... Aperture^66#2

The numerical aperture $\mathit{NA}$ of a lens is the sine of its half acceptance angle $\alpha$, i.e., $\mathit{NA} = \sin(\alpha/2)$.