5.1 Layout Interface

The input data interface assumes two optional input formats of the layout data:

1. GDSII-Format: Binary format where the mask layers are identified only by an integer number between 1 and 64 (Advantage: Very compact / Disadvantage: Readable only by specialized layout viewers)

2. CIF-Format (Caltech Interchange Format): ASCII format identifying the mask layers by alphanumeric names (Advantage: Readable by any text editor / Disadvantage: Huge size for bigger layouts)

Since in semiconductor fabrication the mask layers are normally identified by alphanumeric names (like AA for active area mask) and the layout input for process simulations consists normally of only a very limited number of devices (typically one or two per simulation run) the CIF format was chosen as the standard input format due to the above mentioned advantages.

The GDS-layout input is initially converted to CIF-format by using a process node specific lookup-table which refers between the GDSII layer numbers and the mask level names.

In the Synopsys TCAD toolset the CIF-format is then transformed as described in Section 3.3.2 by setting up the mask transformations in a command file which is specific to the semiconductor process flow in scope. This setup file is only defined once in the development phase of the process and never change through the life cycle of the semiconductor process (otherwise every layout would have to be changed according to the modifications). An example for such mask generation instructions has been given in Table 4.1. The layout transformation is performed by simply starting the PROLYT layout tool in batch mode. Since normally not the whole layout of a device has to be simulated, only a selected portion of the device is defined in the layout and the according positional information and a name for this region definition is saved into the CIF-layout representation as additional layers recognized by the process flow simulator. The layer name identifies the dedicated simulation region. Therefore multiple simulation regions may be defined in a single layout. Finally the positions where measurements should be carried out during the process flow are marked as one-dimensional regions on the layout.
Optionally an aerial image simulation can be performed to generate mask information matching more closely the real shapes of the photo resist. Examples for such a preprocessing step can be found in Figure 3.5 in Section 3.3.2 and in Figure 6.6 and Figure 6.7 in Section 6.3. This preprocessing is mandatory, if capacitance coupling effects or crosstalk play an important role in the simulated structure. For instance the exact shape of the floating gate has to be resolved with high accuracy to calculate the exact coupling ratio of a tunneling EEPROM device as shown in Section 6.3.2.

This mask position and dimension information is passed automatically to the process simulator and defines the position and shape of the photo resist masks during the lithography simulation steps.