There are three major sources of mechanical stress in passivated interconnect lines. The first is the thermal stress, resulting from the difference in thermal expansion between the passivation and metal upon cooling from high deposition temperatures. Metalization processing can expose an integrated circuit to temperatures of more than 500 C. The second source of stress is nonequilibrium film growth. As wafer curvature measurements have shown, this source of stress is even more important than the thermal stress. The third major source of stress is the electromigration itself. Although the measurements significantly contribute to the understanding of thin film stresses, they are, in most cases, limited to simple test structures. Furthermore, the detailed stress distribution within a material cannot be experimentally determined. For the dual-damascene technology high tensile stresses at interfaces, such as in the metal/capping layer interface, are generally critical, and electromigration can either increase or reduce this local tensile stress.
The choice of passivating film material and corresponding process technology causes tensile or compressive stress in the interface between the passivating film and the interconnect metal. Interfacial compressive stress diminishes electromigration along interfaces by reducing the diffusivity . However, numerous experimental observations have shown that tensile stress in the interface increases the possibility of failure . Increased thickness and rigidity of the capping layer prevent relaxation of both thermal and electromigration induced stress, which results in dielectric cracking and metal extrusion.
The evolution of mechanical stress in interconnect lines depends on whether or not vacancies can be created or annihilated such that their equilibrium is maintained. For mechanical stresses to develop, there must be both a volume expansion or contraction of the line with respect to the surrounding material and a mechanical constraint applied by the surrounding material. As atoms exchange place with vacancies and travel towards the anode end of the line, there is a flow of vacancies towards the cathode end. In the absence of vacancy sources and sinks, this would result in a vacancy supersaturation on the cathode end and a deficiency at the anode end. Since there is a small relaxation of the lattice surrounding a vacancy, vacancy accumulation would produce volume contraction at the cathode. In turn, the depletion of vacancies would produce volume expansion at the anode end. However, due to the constraints imposed by the surrounding layers, namely, the capping layer, the barrier layer, and the passivation in copper dual-damascene interconnects, these volumetric changes cannot be accommodated, which results in the development of mechanical stress in the line. At the cathode end tensile stress is produced, while compressive stress develops at the anode end of the line. As will be shown below, this stress gradient acts as an additional driving force for material transport and must be taken into account in the vacancy flux equation. Moreover, mechanical stress is a key parameter for the void nucleation condition.