The layout of the DRAM cell discussed above consisted only of rectangles. Therefore the structure could be easily generated without the interactive layout editor, just using the primitives provided by the solid modeling tool. We now address an example, where the different layers cannot be defined anymore by geometric primitives. The layout of a two metal layer interconnect example is shown in Fig. 4.3 and consists of a set of L-shaped polygons. It is obvious that these polygons are also feasible with the combination of two rectangles, but this is not a very foreseeable method, and recommends the more intuitive way of composing the layout with the interactive editor depicted in Fig. 4.3. The two-dimensional layout is again expanded to a three-dimensional structure. The following process flow uses the etching and deposition steps introduced in Section 3.2 and broadens the application of the morphological operations to the modeling of etching and deposition steps.
Let's take a look at the single steps in the process. First of all, the size of the simulation domain has to be defined. A domain of with the silicon dioxide surface in green, positioned close to the lower limit of the domain [Fig. 4.4(b)] assures enough space for the following deposition steps and is generated with the procedure presented in Section 3.1.1. The next steps are the deposition of a blanket aluminium layer [dark blue in Fig. 4.4(c)] and the application of a patterned resist mask [yellow in Fig. 4.4(d)] with the procedure introduced in Section 3.1.2. For the first metal layer the two dark blue polygons are selected from the layout in Fig. 4.4(a). With a directional etching step, the resist pattern is etched downwards into the aluminum layer [Fig. 4.4(e)]. The resist can be stripped afterwards [Fig. 4.4(f)], which is followed by the deposition of oxide forming the isolation between the two metalization levels [Fig. 4.5(a)]. This process step is simulated with isotropic deposition, forming the first non-planar layer and a strongly curved surface for the following resist mask.
The structure generated so far works as substrate for the second metal layer. Again a blanket aluminium layer is isotropically deposited [light blue in Fig. 4.5(b)]. The resist mask [yellow in Fig. 4.5(c)] is applied to the non-planar surface, using the two light blue, L-shaped polygons from Fig. 4.4(a). The directional etching step [Fig. 4.5(d)] again transfers the resist pattern to the metal. The second resist layer has fulfilled its task and can be stripped [Fig. 4.5(e)]. The second oxide layer, again isotropically deposited, merges with the first one and encapsulates the two metal levels [Fig. 4.5(f)]. By these means an accurate solid model of the interconnect structure is obtained and ready to be transfered to the capacitance extraction tool for interconnect characterization.
Two aspects of the aluminium layer formation have to be addressed. The first one is, that the solid modeling tools would also allow to deposit an aluminium layer directly patterned with the polygons from the layout. Nevertheless, the three-step patterning procedure which uses the intermediate resist film is chosen for imitating the real process as close as possible and in order to demonstrate the facilities of the combined solid modeling and topography simulation approach. The shared file format allows switching between solid modeling and accurate simulation of etching and deposition before any step in the simulation flow, granting appropriate speed and accuracy for each process step.
Secondly, the absolutely correct way to obtain the resist mask is blanket resist spin-on, illumination, exposure, and development. These aspects of the lithography process, which are in close relation with the solid modeling approach will be illuminated in the following section.
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