previous up next contents
Prev: Two Metal Layer Up: 4. Inclusion of Layout Next: 4.2.1 Interconnect Example

4.2 Inclusion of Lithography Simulation

Solid modeling with patterns taken directly from the layout does not account for the differences between the chip design and the patterns appearing on the wafer after lithographic projection. Therefore it is desirable to include lithography simulation into the solid modeling and topography simulation procedure.

Lithography simulation usually splits up into three steps. The first step deals with the optical pathway of the projection which transfers the layout to an aerial image formed at the wafer surface. The subsequent exposure step calculates how the pattern given in the aerial image propagates downwards into the resist. The calculation relies on the solution of the Maxwell equations which describe the propagation of the light as electro-magnetic field. The aerial image serves as boundary condition for the solution of the Maxwell equations. The last step of a lithography process is the development of the resist profile which emerges according to the inhomogeneous properties of the resist caused by the light intensity modulated by the layout patterns.

The three steps have different consequences for the final shape of the patterns on the wafer. In contrast to the aerial image which represents the layout patterns on the wafer surface, exposure simulation accounts for scattering and reflection phenomena within the resist, which lead to standing wave effects on the resist sidewalls. When the line width is comparable with the wavelength used for the illumination, these reflection effects which lead to non-vertical sidewalls are of significant importance and have to be included, as will be demonstrated later in Chapter 5. For the larger structures addressed here within the scope of geometry generation, the aerial image formation has the predominant influence on the patterns and it is arguable to neglect the sidewall effects. The expansion of the layout inclusion to handling of aerial images will be demonstrated with the following example.

Subsections previous up next contents
Prev: Two Metal Layer Up: 4. Inclusion of Layout Next: 4.2.1 Interconnect Example

W. Pyka: Feature Scale Modeling for Etching and Deposition Processes in Semiconductor Manufacturing