The layout from Fig. 4.1 shows the layers necessary for the description of the manufacturing process for the DRAM cell. It comprises the definition of the trench capacitor, of active areas, and of POLY lines as well as METAL lines.
Fig. 4.2 opposes the structures resulting from the two different methods applied to the generation of the DRAM geometry. For both cases the trench capacitor buried in the silicon was simulated with the same sequence of trench etching, deposition of the dielectric dioxide, and filling of the trench. The dark area on the left hand side of the mesh-based geometry shows the very fine mesh necessary to resolve the rounded corners and the thin oxide layer of the trench capacitor. The difference of the two structures lies in the interconnect part on top of the silicon substrate, which is simulated with two different methods.
The first method is a strictly geometric, layer-based mesh generation . It composes the structure by assigning planar material layers with a specified thickness to the polygons from the layout and by stacking these planar layers. Materials, thicknesses, symbolic and net names as well as external current or potential boundary conditions which are defined in the layout file and accessible for both methods in the same way are assigned during the stacking process.
In order to obtain a consistent three-dimensional mesh, the floor plan joining all mask layers is triangulated. The triangulation is possible with two different strategies  and used in the next stage for the formation of prismatic cells according to the thickness of the single layers. Since the triangulation comprises all polygons, the connectivity of subsequent layers is guaranteed. Finally the prismatic cells are split into tetrahedral elements. The resulting mesh is depicted on the left hand side of Fig. 4.2. The figure also shows the major drawback of this method. Due to the simultaneous triangulation of all layers, the dense mesh required in order to resolve the thin oxide layer of the trench is continued throughout the interconnect layers on top of the silicon substrate, wasting valuable computational resources in areas where such a fine resolution is not necessary.
The second method for the generation of the interconnect structure is accurate topography simulation including masks applied with the solid modeling strategy introduced in the previous chapter. The layers are isotropically deposited on top of the underlying structures and patterned with resist masks applied with the solid modeling program which directly uses the polygons from the layout. A subsequent directional etching step transfers the mask patterns to the underlying POLY layer or METAL layer, and is followed by stripping of the resist. With each new layer the non-planarity of the structure and thus the difference to the layer-based method increases. The result of this approach is mirrored on the right hand side of Fig. 4.2.
Both methods have in common, that they avoid the error-prone specification of the geometric primitives and the painful editing of point and reference lists by directly applying the predefined polygons from the layout. Moreover the structures for both methods can be combined with the accurately simulated trench capacitor in the same way. The decisive factor why the accurate topography simulation is preferred over the layer-based method is, that a subsequent capacitance extraction clearly shows, that only the accurate topography simulation taking into account the non-planarity of the underlying layers leads to results which are in satisfactory agreement with experimentally measured values for the capacitances. For the presented DRAM example, accurate topography simulation was able to reduce the error of the bit-line capacitance by a factor of 5 with respect to the layer-based method.
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