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5. Resist Development

Photolithography holds the leading position in pattern transfer in today's semiconductor manufacturing. The steady decrease of the minimal feature size reaching the wavelength used for the exposure and effects of non-planar surface scattering push state-of-the-art lithography technologies to their limits. Rigorous three-dimensional simulation tools for illumination as well as exposure assist in better understanding of the optical and physical effects of sub-micron photo-lithography and significantly support research and development aiming at higher resolution and better depth of focus over non-planar surfaces.

Resist development is the last step of a photo-lithography process and responsible for the resist profile emerging from the intensity distribution appearing during exposure. Resist development is carried out with chemical wet etching processes. Development can be modeled as isotropic etching process, where the etch rate is correlated with the spatially inhomogeneous dissolution rate of the resist. Depending on the type of resist, different chemical systems are used to amplify the reactions of the photo-active components, which are triggered during exposure.

This chapter describes how the structuring element algorithm is applied to the modeling of resist development. The model itself will be introduced in Section 5.1 recapitulating the cellular data representation as well as the structuring element algorithm. Particular emphasis will be put on illustrating the special adjustments for the resist development model. In Section 5.2 several test examples which are prototypical for development simulations will be introduced. The benchmark examples are used as auxiliary means in order to exemplify general aspects for three-dimensional topography simulation such as self intersection of emerging fronts and possible loop formations leading to undefined surface normals. Accuracy and robustness of the presented approach will be discussed as well. Section 5.3 finally demonstrates how the topography simulation is coupled with a rigorous lithography simulation method presented in [32][33].

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W. Pyka: Feature Scale Modeling for Etching and Deposition Processes in Semiconductor Manufacturing