2.1.1.2 Etching and Deposition

After the structural information has been transferred to the wafer's surface by means of lithography, this wafer undergoes some etching process which makes the prescribed structure -- represented by photo-resistant material -- permanent. Unless this operation is not also modeled using unphysical pseudo models it can be done with PROMIS-ETCH [65,87], SC-TOP [81], or the simulator developed by Bär and Lorenz [3]. These tools are able to model the etching and the deposition operation in the sequence of Figure 2.2.

Accurate modeling of etching and deposition is particularly necessary for the formation of spacers between the gate area and the source drain regions of a CMOS device [102] (see Figure 2.3). Since the geometric dimensions of this spacers implicitly define the effective channel length of the resulting devices, good accuracy is highly desirable in this area. Another processing technique where accurate topography modeling is critical is the formation of shallow trenches [79] for isolation purposes which becomes necessary for future fabrication technologies.